Cyclone® V to Agilex™ 5 Device Migration Guide

Download PDF
ID 787947
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Device Migration Considerations 3. Intel Quartus Prime and Platform Designer Migration Guidelines 4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide
2. Device Migration Considerations x
2.1. Device Footprint 2.2. Power Management 2.3. Configuration 2.4. Design Security Differences 2.5. Logic Elements and Embedded Memory 2.6. PLL and Clock Network 2.7. Digital Signal Processing (DSP) 2.8. I/O Interfaces 2.9. LVDS SERDES Interface 2.10. Sensor Monitoring System 2.11. MIPI D-PHY Interface 2.12. External Memory Interface (EMIF) 2.13. Hard Processor System (HPS) 2.14. Transceiver and Serial Protocols 2.15. PCIe Interface 2.16. Ethernet Interface
2.3. Configuration x
2.3.1. General Configuration Pin and Sequences 2.3.2. Device Configuration and the Secure Device Manager (SDM) 2.3.3. Active Serial (AS) Configuration 2.3.4. Avalon® -ST Configuration 2.3.5. JTAG Configuration 2.3.6. Configuration via Protocol (CvP) 2.3.7. QSPI Flash Access and Remote System Upgrade Feature 2.3.8. SEU Features 2.3.9. Configuration File Format Differences
2.8. I/O Interfaces x
2.8.1. HSIO Bank 2.8.2. HPS I/O Bank 2.8.3. SDM I/O Bank 2.8.4. HVIO Bank
2.13. Hard Processor System (HPS) x
2.13.1. HPS Boot Flows
2.14. Transceiver and Serial Protocols x
2.14.1. PMA Architecture 2.14.2. PCS Architecture 2.14.3. Transceiver Clocking 2.14.4. Transceiver Reset
3. Intel Quartus Prime and Platform Designer Migration Guidelines x
3.1. Overview 3.2. IP Comparison Between Cyclone® V and Agilex™ 5 Devices 3.3. Upgrading IP Cores and Platform Designer Systems 3.4. RTL Compliance
3.3. Upgrading IP Cores and Platform Designer Systems x
3.3.1. Upgrading IP Cores via Quartus® Prime Software Project 3.3.2. Upgrading IP Cores in Platform Designer 3.3.3. Migrating IP Cores to a Different Device
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device x
4.1. Prerequisites 4.2. Downloading and Extracting the Design Example 4.3. Migrating the Design Example
4.3. Migrating the Design Example x
4.3.1. Restoring an Archived Cyclone® V Design in the QAR Format 4.3.2. Specifying an Agilex™ 5 Device 4.3.3. Upgrading IP Cores 4.3.4. Establishing Connections 4.3.5. Compiling the Design
1. Overview
2. Device Migration Considerations
3. Intel Quartus Prime and Platform Designer Migration Guidelines
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device
A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide

3.3. Upgrading IP Cores and Platform Designer Systems

To migrate your designs from Quartus® Prime Standard Edition to Quartus® Prime Pro Edition, you must upgrade all IP cores and Platform Designer systems.

Quartus® Prime Standard Edition, Quartus® Prime Lite Edition, and the legacy Quartus® II design software products use a proprietary Verilog configuration scheme within the top-level of IP cores and Platform Designer systems for file synthesis. However, the Quartus® Prime Pro Edition does not support this scheme. The following table lists the main differences between the Quartus® Prime software editions:

Table 35.  Differences Between Quartus® Prime Software Editions
Quartus® Prime Standard Edition, Quartus® Prime Lite Edition, and the legacy Quartus® II Design Software Quartus® Prime Pro Edition
The proprietary Verilog HDL configuration scheme prevents RTL entities from ambiguous instantiation errors during synthesis. However, these errors may manifest in simulation. Resolving this issue requires one of the following:
  • Write a Verilog HDL configuration to disambiguate the instantiation.
  • Delete the duplicate entity from the project.
  • Rename one of the conflicting entities.

IP and Platform Designer system generation do not use proprietary Verilog HDL configurations and, thus, resolves the issue. The compilation library scheme changes in the following ways:

  • Compiles all variants of an IP core into the same compilation library across the entire project. Quartus® Prime Pro Edition identically names IP cores with identical functionality and parameterization to avoid ambiguous entity instantiation errors.
  • Simulation and synthesis file sets for IP cores and systems instantiate entities similarly.
  • The generated RTL directory structure matches the compilation library structure.

Section Content
Upgrading IP Cores via Quartus Prime Software Project
Upgrading IP Cores in Platform Designer
Migrating IP Cores to a Different Device

Level Two Title