Cyclone® V to Agilex™ 5 Device Migration Guide

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ID 787947
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Device Migration Considerations 3. Intel Quartus Prime and Platform Designer Migration Guidelines 4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide
2. Device Migration Considerations x
2.1. Device Footprint 2.2. Power Management 2.3. Configuration 2.4. Design Security Differences 2.5. Logic Elements and Embedded Memory 2.6. PLL and Clock Network 2.7. Digital Signal Processing (DSP) 2.8. I/O Interfaces 2.9. LVDS SERDES Interface 2.10. Sensor Monitoring System 2.11. MIPI D-PHY Interface 2.12. External Memory Interface (EMIF) 2.13. Hard Processor System (HPS) 2.14. Transceiver and Serial Protocols 2.15. PCIe Interface 2.16. Ethernet Interface
2.3. Configuration x
2.3.1. General Configuration Pin and Sequences 2.3.2. Device Configuration and the Secure Device Manager (SDM) 2.3.3. Active Serial (AS) Configuration 2.3.4. Avalon® -ST Configuration 2.3.5. JTAG Configuration 2.3.6. Configuration via Protocol (CvP) 2.3.7. QSPI Flash Access and Remote System Upgrade Feature 2.3.8. SEU Features 2.3.9. Configuration File Format Differences
2.8. I/O Interfaces x
2.8.1. HSIO Bank 2.8.2. HPS I/O Bank 2.8.3. SDM I/O Bank 2.8.4. HVIO Bank
2.13. Hard Processor System (HPS) x
2.13.1. HPS Boot Flows Key Differences in the HPS Boot Flows HPS-based RSU Flow Differences in the HPS Image Generation Flow
2.14. Transceiver and Serial Protocols x
2.14.1. PMA Architecture 2.14.2. PCS Architecture 2.14.3. Transceiver Clocking 2.14.4. Transceiver Reset
3. Intel Quartus Prime and Platform Designer Migration Guidelines x
3.1. Overview 3.2. IP Comparison Between Cyclone® V and Agilex™ 5 Devices 3.3. Upgrading IP Cores and Platform Designer Systems 3.4. RTL Compliance
3.3. Upgrading IP Cores and Platform Designer Systems x
3.3.1. Upgrading IP Cores via Quartus® Prime Software Project 3.3.2. Upgrading IP Cores in Platform Designer 3.3.3. Migrating IP Cores to a Different Device
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device x
4.1. Prerequisites 4.2. Downloading and Extracting the Design Example 4.3. Migrating the Design Example
4.3. Migrating the Design Example x
4.3.1. Restoring an Archived Cyclone® V Design in the QAR Format 4.3.2. Specifying an Agilex™ 5 Device 4.3.3. Upgrading IP Cores 4.3.4. Establishing Connections 4.3.5. Compiling the Design
1. Overview
2. Device Migration Considerations
3. Intel Quartus Prime and Platform Designer Migration Guidelines
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device
A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide

2.13.1. HPS Boot Flows

The following table outlines different HPS boot flow supported for Cyclone® V and Agilex™ 5. You can use one of the boot flows listed. Direct migration of the boot flow solution from Cyclone® V SoC to Agilex™ 5 SoC is not possible due to architectural differences.

The following table compares the HPS boot flows in Cyclone® V and Agilex™ 5 devices:

Table 23.  HPS Boot Flows Comparison Between Cyclone® V and Agilex™ 5 Devices
HPS Boot Flow Options Start Initialization Boot Stage 1 Boot Stage 2 OS Application
Cyclone® V Power-On Reset Boot ROM Preloader U-Boot Loader Linux Application
Power-On Reset Boot ROM Preloader U-Boot Loader RTOS / Baremetal Application
Power-On Reset Boot ROM Preloader   RTOS / Baremetal Application
Power-On Reset Boot ROM     RTOS / Baremetal Application
Agilex™ 5 Power-On Reset SDM (CMF) U-Boot SPL ATF BL31 and

U-Boot Proper

 Linux Application
Power-On Reset SDM (CMF) ATF BL2 ATF BL31 Linux Application
Power-On Reset SDM (CMF) ATF BL2 ATF BL31 Zephyr Application
Power-On Reset SDM (CMF) ATF BL2 ATF BL31 RTOS / Baremetal Application

Key Differences in the HPS Boot Flows

  • For Cyclone® V, the first software stage is the boot ROM. The boot ROM code locates and executes the second software stage, called the preloader. The preloader locates, and if present, executes the next software stage.

    Supported boot schemes:

    • The HPS boot and FPGA configuration occur separately.
    • The HPS boots first and then configures the FPGA.
    • The HPS boots from the FPGA after the FPGA is configured.
  • For Agilex™ 5, the Secure Device Manager (SDM) manages the secure boot process. Upon a Power-On Reset (POR), the Configuration Management Firmware (CMF) loads the FSBL (U-Boot SPL or ATF BL2) into the HPS On-Chip RAM and brings the HPS boot core out from reset, which executes the next software stage.

    Supported boot schemes:

    • The HPS boots first and then configures the FPGA.
      • Configuring the FPGA fabric from U-Boot.
      • Configuring the FPGA fabric from Linux.
    • The HPS boots from the FPGA after the FPGA is configured.

HPS-based RSU Flow

Cyclone® V devices use the Remote Update Intel® FPGA IP to manage the RSU boot flow, Agilex™ 5 devices use the SDM to manage the RSU boot flow. For more information, refer to the Remote Update Intel® FPGA IP User Guide .

Differences in the HPS Image Generation Flow

In Cyclone® V devices, the cv_bsp_generator.py script processes the hand-off files from the Quartus® Prime software and converts them to source code usable by U-Boot. To use the script, refer to the "Running CV BSP Generator to Process Handoff Files" section in the Cyclone® V SoC GSRD.

For Agilex™ 5, this procedure is not required as the hand-off files are generated and integrated into the bitstream, which is the SOF file in the Quartus® Prime software during project compilation.

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