Cyclone® V to Agilex™ 5 Device Migration Guide

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ID 787947
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Device Migration Considerations 3. Intel Quartus Prime and Platform Designer Migration Guidelines 4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide
2. Device Migration Considerations x
2.1. Device Footprint 2.2. Power Management 2.3. Configuration 2.4. Design Security Differences 2.5. Logic Elements and Embedded Memory 2.6. PLL and Clock Network 2.7. Digital Signal Processing (DSP) 2.8. I/O Interfaces 2.9. LVDS SERDES Interface 2.10. Sensor Monitoring System 2.11. MIPI D-PHY Interface 2.12. External Memory Interface (EMIF) 2.13. Hard Processor System (HPS) 2.14. Transceiver and Serial Protocols 2.15. PCIe Interface 2.16. Ethernet Interface
2.3. Configuration x
2.3.1. General Configuration Pin and Sequences 2.3.2. Device Configuration and the Secure Device Manager (SDM) 2.3.3. Active Serial (AS) Configuration 2.3.4. Avalon® -ST Configuration 2.3.5. JTAG Configuration 2.3.6. Configuration via Protocol (CvP) 2.3.7. QSPI Flash Access and Remote System Upgrade Feature 2.3.8. SEU Features 2.3.9. Configuration File Format Differences
2.8. I/O Interfaces x
2.8.1. HSIO Bank 2.8.2. HPS I/O Bank 2.8.3. SDM I/O Bank 2.8.4. HVIO Bank
2.13. Hard Processor System (HPS) x
2.13.1. HPS Boot Flows
2.14. Transceiver and Serial Protocols x
2.14.1. PMA Architecture 2.14.2. PCS Architecture 2.14.3. Transceiver Clocking 2.14.4. Transceiver Reset
3. Intel Quartus Prime and Platform Designer Migration Guidelines x
3.1. Overview 3.2. IP Comparison Between Cyclone® V and Agilex™ 5 Devices 3.3. Upgrading IP Cores and Platform Designer Systems 3.4. RTL Compliance
3.3. Upgrading IP Cores and Platform Designer Systems x
3.3.1. Upgrading IP Cores via Quartus® Prime Software Project 3.3.2. Upgrading IP Cores in Platform Designer 3.3.3. Migrating IP Cores to a Different Device
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device x
4.1. Prerequisites 4.2. Downloading and Extracting the Design Example 4.3. Migrating the Design Example
4.3. Migrating the Design Example x
4.3.1. Restoring an Archived Cyclone® V Design in the QAR Format 4.3.2. Specifying an Agilex™ 5 Device 4.3.3. Upgrading IP Cores 4.3.4. Establishing Connections 4.3.5. Compiling the Design
1. Overview
2. Device Migration Considerations
3. Intel Quartus Prime and Platform Designer Migration Guidelines
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device
A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide

2.6. PLL and Clock Network

PLL

Direct PLL migration between Cyclone® V and Agilex™ 5 devices is not possible because of the architectural differences between these two device families.

Agilex™ 5 devices contain the following types of I/O PLLs for core application:

  • I/O bank I/O PLL
  • Fabric-feeding I/O PLL

However, the Quartus® Prime software determines the I/O PLL type automatically based on the assigned location of the I/O PLL in the Assignment Editor.

The following table compares supported features between Cyclone® V and Agilex™ 5 devices:

Table 11.   Comparison of Supported Features Between Cyclone® V and Agilex™ 5 Devices
Features Cyclone® V Devices Agilex™ 5 Devices
Integer PLL Supported Supported
Fractional PLL Supported Not supported
C Counter Output 9
  • Four for I/O bank I/O PLL
  • Seven for Fabric-feeding I/O PLL
Dedicated External Clock Output Supported Supported 1
External Feedback Input Pin Supported Supported1
Source Synchronous Compensation Supported Supported
Direct Compensation Supported Supported
Normal Compensation Supported Supported
Zero-delay Buffer Compensation Supported Supported1
External Feedback Compensation Supported Supported1
LVDS Compensation Supported Supported1
Programmable Duty Cycle Supported Supported
Bandwidth Settings Low, Medium, High Automatically selected by the Quartus® Prime software
Dynamic Phase Shift
  • PLL reconfiguration IP
  • Altera PLL IP
 PLL reconfiguration IP only
PLL Cascading Supported Supported 2
Output Counter Cascading Supported Not supported
Input Clock Switchover Supported Supported2

Due to the differences between Cyclone® V and Agilex™ 5 devices, you must identify if Agilex™ 5 devices support the PLL feature when planning to migrate from Cyclone® V devices. For example, Agilex™ 5 devices do not support fractional PLL, so if you need to use this feature for transceiver application, use transceiver PLL (TX PLL). For more information, refer to the Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs.

Clock Network

The clock network architecture in Agilex™ 5 devices differ from Cyclone® V device architecture. Agilex™ 5 devices do not have Regional Clock (RCLK) and Periphery Clock (PCLK) networks. The Quartus® Prime Pro Edition software automatically determines the clock regions.

Agilex™ 5 devices use programmable clock tree synthesis for its core clocking function. Programmable clock tree synthesis uses dedicated clock tree routing and switching circuits. These dedicated circuits enable the Quartus® Prime Pro Edition software to create the clock trees your design requires.

Related Information
1 Feature supported by I/O bank I/O PLL only. Not supported by Fabric-feeding I/O PLL.
2 Feature not supported by the Fabric-feeding I/O PLL located in the High Voltage I/O (HVIO) block.
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