Cyclone® V to Agilex™ 5 Device Migration Guide

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ID 787947
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Device Migration Considerations 3. Intel Quartus Prime and Platform Designer Migration Guidelines 4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide
2. Device Migration Considerations x
2.1. Device Footprint 2.2. Power Management 2.3. Configuration 2.4. Design Security Differences 2.5. Logic Elements and Embedded Memory 2.6. PLL and Clock Network 2.7. Digital Signal Processing (DSP) 2.8. I/O Interfaces 2.9. LVDS SERDES Interface 2.10. Sensor Monitoring System 2.11. MIPI D-PHY Interface 2.12. External Memory Interface (EMIF) 2.13. Hard Processor System (HPS) 2.14. Transceiver and Serial Protocols 2.15. PCIe Interface 2.16. Ethernet Interface
2.3. Configuration x
2.3.1. General Configuration Pin and Sequences 2.3.2. Device Configuration and the Secure Device Manager (SDM) 2.3.3. Active Serial (AS) Configuration 2.3.4. Avalon® -ST Configuration 2.3.5. JTAG Configuration 2.3.6. Configuration via Protocol (CvP) 2.3.7. QSPI Flash Access and Remote System Upgrade Feature 2.3.8. SEU Features 2.3.9. Configuration File Format Differences
2.8. I/O Interfaces x
2.8.1. HSIO Bank 2.8.2. HPS I/O Bank 2.8.3. SDM I/O Bank 2.8.4. HVIO Bank
2.13. Hard Processor System (HPS) x
2.13.1. HPS Boot Flows
2.14. Transceiver and Serial Protocols x
2.14.1. PMA Architecture 2.14.2. PCS Architecture 2.14.3. Transceiver Clocking 2.14.4. Transceiver Reset
3. Intel Quartus Prime and Platform Designer Migration Guidelines x
3.1. Overview 3.2. IP Comparison Between Cyclone® V and Agilex™ 5 Devices 3.3. Upgrading IP Cores and Platform Designer Systems 3.4. RTL Compliance
3.3. Upgrading IP Cores and Platform Designer Systems x
3.3.1. Upgrading IP Cores via Quartus® Prime Software Project 3.3.2. Upgrading IP Cores in Platform Designer 3.3.3. Migrating IP Cores to a Different Device
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device x
4.1. Prerequisites 4.2. Downloading and Extracting the Design Example 4.3. Migrating the Design Example
4.3. Migrating the Design Example x
4.3.1. Restoring an Archived Cyclone® V Design in the QAR Format 4.3.2. Specifying an Agilex™ 5 Device 4.3.3. Upgrading IP Cores 4.3.4. Establishing Connections 4.3.5. Compiling the Design
1. Overview
2. Device Migration Considerations
3. Intel Quartus Prime and Platform Designer Migration Guidelines
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device
A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide

3.3.1. Upgrading IP Cores via Quartus® Prime Software Project

Any Intel® FPGA IP variations that you generate from a previous version or different edition of the Quartus® Prime software may require an upgrade before compiling in the current software edition or version. This is also true for the design migration from Cyclone® V to Agilex™ 5 devices.

Once you open a design created using Quartus® Prime Standard Edition in the Quartus® Prime Pro Edition, the software prompts you to choose a new device family that the Quartus® Prime Pro Edition software supports, as the Cyclone® V device is not available in the Quartus® Prime Pro Edition, as shown in the following image:

Figure 8. Select Family Dialog Box in the Quartus® Prime Pro Edition Software

As shown in the following image, the Project Navigator displays a banner indicating the IP upgrade status. Click Launch IP Upgrade Tool or Project > Upgrade IP Components to upgrade the outdated IP cores:

Figure 9. IP Upgrade Banner and the Project Navigator

To upgrade IP cores, perform these steps:

  1. In the latest version of the Quartus® Prime Pro Edition software, open the Quartus® Prime project containing an outdated IP core variation. The Upgrade IP Components dialog box automatically displays the status of IP cores in your project, along with instructions for upgrading each core. To access this dialog box manually, click Project > Upgrade IP Components.
  2. To upgrade one or more IP cores that support automatic upgrade, enable the Auto Upgrade checkbox for the IP cores and click Auto Upgrade. The Status and Version columns update when the upgrade is complete. Example designs that any Intel FPGA IP core provides regenerate automatically whenever you upgrade an IP core.
  3. To manually upgrade an individual IP core, select the IP core and click Upgrade in Editor or double-click the IP core name. The parameter editor opens, allowing you to adjust parameters and regenerate the latest version of the IP core.
Note: Upgrading IP cores may append a unique identifier to the original IP core entity names without similarly modifying the IP instance name. There is no requirement to update these entity references in any supporting Quartus® Prime files, such as the Quartus® Prime Settings File (.qsf), Synopsys* Design Constraints File (.sdc), or Signal Tap file (.stp) if these files contain instance names. The Quartus® Prime software reads only the instance name and ignores the entity name in paths that specify both names. Use only instance names in assignments.
Note: You cannot upgrade IP cores instantiated in the Quartus® Prime Pro Edition software version 23.2.1 to 23.4. Regenerate the instantiated IPs to proceed with your project. However, IP auto-upgrade will upgrade IPs from 23.4 to 24.3 and later releases.

Icons in the Upgrade IP Components dialog box indicate when an IP upgrade is required, optional, or unsupported for an IP variation in the project. Upgrade IP variations require an upgrade before compilation in the current version of the Quartus® Prime software. Hover over the icons left to the Auto Upgrade column to view the IP core status.

The following table lists IP core statuses that you can observe in the Upgrade IP Components dialog box, along with their meanings:

Table 36.  IP Core Statuses and Their Meanings
IP Core Status Description
IP Component Up to Date Indicates that your IP variation uses the latest Intel FPGA IP core version.
IP Component is Outdated Indicates that your IP variation uses an outdated IP core version.
IP End of Life Indicates that Intel has designated the IP core with end-of-life status. You may or may not be able to edit the IP core in the parameter editor. Support for this IP core discontinues in the future Quartus® Prime software releases.
IP Upgrade Mismatch Warning Provides warning for non-critical IP core differences when migrating IP to another device family.
IP has incompatible subcores Indicates that the current version of the Quartus® Prime software does not support compilation of your IP variation because the IP has incompatible subcores.
Compilation of IP Not Supported Indicates that the current version of the Quartus® Prime software does not support the compilation of your IP variation. This can occur if another edition of the Quartus® Prime software, such as the Quartus® Prime Standard Edition, generated this IP. Replace this IP component with a compatible component in the current edition.
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