Cyclone® V to Agilex™ 5 Device Migration Guide

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ID 787947
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Device Migration Considerations 3. Intel Quartus Prime and Platform Designer Migration Guidelines 4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide
2. Device Migration Considerations x
2.1. Device Footprint 2.2. Power Management 2.3. Configuration 2.4. Design Security Differences 2.5. Logic Elements and Embedded Memory 2.6. PLL and Clock Network 2.7. Digital Signal Processing (DSP) 2.8. I/O Interfaces 2.9. LVDS SERDES Interface 2.10. Sensor Monitoring System 2.11. MIPI D-PHY Interface 2.12. External Memory Interface (EMIF) 2.13. Hard Processor System (HPS) 2.14. Transceiver and Serial Protocols 2.15. PCIe Interface 2.16. Ethernet Interface
2.3. Configuration x
2.3.1. General Configuration Pin and Sequences 2.3.2. Device Configuration and the Secure Device Manager (SDM) 2.3.3. Active Serial (AS) Configuration 2.3.4. Avalon® -ST Configuration 2.3.5. JTAG Configuration 2.3.6. Configuration via Protocol (CvP) 2.3.7. QSPI Flash Access and Remote System Upgrade Feature 2.3.8. SEU Features 2.3.9. Configuration File Format Differences
2.8. I/O Interfaces x
2.8.1. HSIO Bank 2.8.2. HPS I/O Bank 2.8.3. SDM I/O Bank 2.8.4. HVIO Bank
2.13. Hard Processor System (HPS) x
2.13.1. HPS Boot Flows
2.14. Transceiver and Serial Protocols x
2.14.1. PMA Architecture 2.14.2. PCS Architecture 2.14.3. Transceiver Clocking 2.14.4. Transceiver Reset
3. Intel Quartus Prime and Platform Designer Migration Guidelines x
3.1. Overview 3.2. IP Comparison Between Cyclone® V and Agilex™ 5 Devices 3.3. Upgrading IP Cores and Platform Designer Systems 3.4. RTL Compliance
3.3. Upgrading IP Cores and Platform Designer Systems x
3.3.1. Upgrading IP Cores via Quartus® Prime Software Project 3.3.2. Upgrading IP Cores in Platform Designer 3.3.3. Migrating IP Cores to a Different Device
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device x
4.1. Prerequisites 4.2. Downloading and Extracting the Design Example 4.3. Migrating the Design Example
4.3. Migrating the Design Example x
4.3.1. Restoring an Archived Cyclone® V Design in the QAR Format 4.3.2. Specifying an Agilex™ 5 Device 4.3.3. Upgrading IP Cores 4.3.4. Establishing Connections 4.3.5. Compiling the Design
1. Overview
2. Device Migration Considerations
3. Intel Quartus Prime and Platform Designer Migration Guidelines
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device
A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide

2.15. PCIe Interface

Agilex™ 5 offers enhanced PCIe* interface support compared to Cyclone® V. However, you cannot directly migrate a PCIe* design from a Cyclone® V device to an Agilex™ 5 device because of architectural differences and the IP used to implement the PCIe* interface.

The following table lists key differences in the PCIe* interface between Cyclone® V and Agilex™ 5 devices:

Table 30.   PCIe* Interface Differences
Feature Cyclone® V Agilex™ 5
IP Configuration Supports PCIe* endpoint and root port up to Gen2 data rate and x4 lane configuration.

Supports PCIe* endpoint, root port, and TLP bypass mode up to Gen4 data rate and x8 lane configuration.

PCIe* Interface Implementation Use either the PCIe* hard IP or PHY IP core for PCI Express* (PIPE).
  • PCIe* hard IP: Offers dedicated hard logic that includes the transaction, data link, and PHY/MAC layers.
  • PIPE mode: Implements PCS and PMA modules for up to Gen2 data rates. You must connect this PHY IP Core for PCI Express* to a third-party PHY MAC in the FPGA fabric to create a complete PCI Express* design.
Use the PCIe* hard IP only. PIPE mode is not supported.
Transceiver reconfiguration controller Connects to the PCIe* hard IP or the PIPE to compensate for the variations due to process, voltage, and temperature. Not required.
Reference clock for the PCIe* hard IP Connects to the mgmt_clk_clk signal of the transceiver reconfiguration controller. A system PLL IP is required to be connected to the PCIe* hard IP to provide the FPGA fabric clock.
Separate Reference Clock

Supports without spread spectrum.

Supports with independent spread spectrum.
PCIe* Channels Placement Follows certain placement guidelines. Constrained by the CMU PLL location and lane 0 of the PCIe* interface. You can implement independent PCIe* interface up to x4 lane width in each transceiver bank and up to x8 lane width in every two transceiver banks.

Avalon® Streaming ( Avalon® -ST) vs AXI Interface

PCIe* interface direct migration between Cyclone® V and Agilex™ 5 E Series devices is not possible because of the difference in the hard IP architecture.

Intel® recommends creating Agilex™ 5 PCIe* interface IP from scratch and not from your existing Cyclone® V design. The PCIe* hard IP application interface in the Cyclone® V device is designed based on the Avalon® -ST protocol, while Agilex™ 5 is designed based on the AXI4-Stream protocol. Hence, you must redesign the user-logic connected to the PCIe* hard IP application interface based on the AXI4-Stream protocol.

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