Cyclone® V to Agilex™ 5 Device Migration Guide

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ID 787947
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Device Migration Considerations 3. Intel Quartus Prime and Platform Designer Migration Guidelines 4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide
2. Device Migration Considerations x
2.1. Device Footprint 2.2. Power Management 2.3. Configuration 2.4. Design Security Differences 2.5. Logic Elements and Embedded Memory 2.6. PLL and Clock Network 2.7. Digital Signal Processing (DSP) 2.8. I/O Interfaces 2.9. LVDS SERDES Interface 2.10. Sensor Monitoring System 2.11. MIPI D-PHY Interface 2.12. External Memory Interface (EMIF) 2.13. Hard Processor System (HPS) 2.14. Transceiver and Serial Protocols 2.15. PCIe Interface 2.16. Ethernet Interface
2.3. Configuration x
2.3.1. General Configuration Pin and Sequences 2.3.2. Device Configuration and the Secure Device Manager (SDM) 2.3.3. Active Serial (AS) Configuration 2.3.4. Avalon® -ST Configuration 2.3.5. JTAG Configuration 2.3.6. Configuration via Protocol (CvP) 2.3.7. QSPI Flash Access and Remote System Upgrade Feature 2.3.8. SEU Features 2.3.9. Configuration File Format Differences
2.8. I/O Interfaces x
2.8.1. HSIO Bank 2.8.2. HPS I/O Bank 2.8.3. SDM I/O Bank 2.8.4. HVIO Bank
2.13. Hard Processor System (HPS) x
2.13.1. HPS Boot Flows
2.14. Transceiver and Serial Protocols x
2.14.1. PMA Architecture 2.14.2. PCS Architecture 2.14.3. Transceiver Clocking 2.14.4. Transceiver Reset
3. Intel Quartus Prime and Platform Designer Migration Guidelines x
3.1. Overview 3.2. IP Comparison Between Cyclone® V and Agilex™ 5 Devices 3.3. Upgrading IP Cores and Platform Designer Systems 3.4. RTL Compliance
3.3. Upgrading IP Cores and Platform Designer Systems x
3.3.1. Upgrading IP Cores via Quartus® Prime Software Project 3.3.2. Upgrading IP Cores in Platform Designer 3.3.3. Migrating IP Cores to a Different Device
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device x
4.1. Prerequisites 4.2. Downloading and Extracting the Design Example 4.3. Migrating the Design Example
4.3. Migrating the Design Example x
4.3.1. Restoring an Archived Cyclone® V Design in the QAR Format 4.3.2. Specifying an Agilex™ 5 Device 4.3.3. Upgrading IP Cores 4.3.4. Establishing Connections 4.3.5. Compiling the Design
1. Overview
2. Device Migration Considerations
3. Intel Quartus Prime and Platform Designer Migration Guidelines
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device
A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide

3.3.3. Migrating IP Cores to a Different Device

To target a different (often newer) device, you must migrate an Intel FPGA IP variation. As Cyclone® V designs use IP cores from Quartus® Prime Standard Edition, not all IP cores support device migration to Quartus® Prime Pro Edition. So, you must replace such IP cores in your project. The Upgrade IP Components dialog box identifies the migration support level for each IP core in the design.

To migrate an IP core to a different device, perform these steps:

  1. Click Project > Upgrade IP Components to display the IP cores that require migration. The Description field provides migration instructions and version differences.
    Automatic-Upgrade Supported IP cores Manual-Upgrade Supported IP Cores
    Enable the Auto Upgrade checkbox for the IP cores and click Automatic Upgrade. The Status and Version columns update when the upgrade is complete. Double-click the IP core name and click OK or click Upgrade in Editor. The parameter editor appears. If the parameter editor specifies a Currently selected device family, turn off Match project/default and select a new target device family.
  2. Click Generate HDL.
  3. Confirm the Synthesis and Simulation file options. Verilog HDL is the default output file format.
  4. If you specify VHDL as the output format, select VHDL to retain the original output format.
  5. Click Finish to complete the IP core migration.
  6. Click OK if the software prompts you to overwrite IP core files. When IP core migration is complete, the Device Family column displays the new target device name.
  7. Review the latest parameters in the parameter editor or generated HDL to ensure correctness.
Note: IP migration may change IP variation's ports, parameters, or functionality. These changes may require you to modify your design or to reparameterize your IP variant. During migration, the IP variation's HDL generates a library different from the IP core's original output location. Update any assignments that reference outdated locations. If a symbol in a supporting Block Design File schematic represents your upgraded IP core, replace the symbol with the newly generated <my_ip>.bsf. Migration of some IP cores requires installed support for the original and migration device families.

If you need to troubleshoot IP or Platform Designer system upgrade, refer to the "Troubleshooting IP or Platform Designer System Upgrade" topic in the Quartus® Prime Pro Edition User Guide: Getting Started.

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