Cyclone® V to Agilex™ 5 Device Migration Guide

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ID 787947
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Device Migration Considerations 3. Intel Quartus Prime and Platform Designer Migration Guidelines 4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide
2. Device Migration Considerations x
2.1. Device Footprint 2.2. Power Management 2.3. Configuration 2.4. Design Security Differences 2.5. Logic Elements and Embedded Memory 2.6. PLL and Clock Network 2.7. Digital Signal Processing (DSP) 2.8. I/O Interfaces 2.9. LVDS SERDES Interface 2.10. Sensor Monitoring System 2.11. MIPI D-PHY Interface 2.12. External Memory Interface (EMIF) 2.13. Hard Processor System (HPS) 2.14. Transceiver and Serial Protocols 2.15. PCIe Interface 2.16. Ethernet Interface
2.3. Configuration x
2.3.1. General Configuration Pin and Sequences 2.3.2. Device Configuration and the Secure Device Manager (SDM) 2.3.3. Active Serial (AS) Configuration 2.3.4. Avalon® -ST Configuration 2.3.5. JTAG Configuration 2.3.6. Configuration via Protocol (CvP) 2.3.7. QSPI Flash Access and Remote System Upgrade Feature 2.3.8. SEU Features 2.3.9. Configuration File Format Differences
2.8. I/O Interfaces x
2.8.1. HSIO Bank 2.8.2. HPS I/O Bank 2.8.3. SDM I/O Bank 2.8.4. HVIO Bank
2.13. Hard Processor System (HPS) x
2.13.1. HPS Boot Flows
2.14. Transceiver and Serial Protocols x
2.14.1. PMA Architecture 2.14.2. PCS Architecture 2.14.3. Transceiver Clocking 2.14.4. Transceiver Reset
3. Intel Quartus Prime and Platform Designer Migration Guidelines x
3.1. Overview 3.2. IP Comparison Between Cyclone® V and Agilex™ 5 Devices 3.3. Upgrading IP Cores and Platform Designer Systems 3.4. RTL Compliance
3.3. Upgrading IP Cores and Platform Designer Systems x
3.3.1. Upgrading IP Cores via Quartus® Prime Software Project 3.3.2. Upgrading IP Cores in Platform Designer 3.3.3. Migrating IP Cores to a Different Device
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device x
4.1. Prerequisites 4.2. Downloading and Extracting the Design Example 4.3. Migrating the Design Example
4.3. Migrating the Design Example x
4.3.1. Restoring an Archived Cyclone® V Design in the QAR Format 4.3.2. Specifying an Agilex™ 5 Device 4.3.3. Upgrading IP Cores 4.3.4. Establishing Connections 4.3.5. Compiling the Design
1. Overview
2. Device Migration Considerations
3. Intel Quartus Prime and Platform Designer Migration Guidelines
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device
A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide

2.9. LVDS SERDES Interface

There are architectural differences between Cyclone® V and Agilex™ 5 devices.

The following table lists differences in the LVDS SERDES interface support between Cyclone® V and Agilex™ 5 devices:

Table 20.  LVDS Interface Support
Feature Cyclone® V Agilex™ 5
Receiver Transmitter Receiver Transmitter
VCCIO_PIO 2.5 V 1.05 V / 1.1 V / 1.2 V / 1.3 V 1.3 V
Data rate 875 Mbps 840 Mbps 1.6 Gbps
I/O standard
  • LVDS
  • SLVS
  • Mini-LVDS
  • RSDS
  • LVDS
  • Mini-LVDS
  • RSDS
  • Emulated LVDS
  • Emulated mini-LVDS
  • Emulated RSDS
  • True differential signaling compatible with:
    • LVDS
    • RSDS
    • SLVS
    • Mini-LVDS
    • LVPECL
  • SLVS400 (871 Mbps)
  • True differential signaling compatible with:
    • LVDS
    • RSDS
    • SLVS
    • Mini-LVDS
SERDES factor 4, 5, 6, 7, 8, 9, 10 4, 8
Note: Intel plans to add support for Gearbox in a future release.
LVDS SERDES supported mode Non-DPA — Soft-CDR, DPA, non-DPA —

The above table shows that an Agilex™ 5 device can support a higher data rate than Cyclone® V and has a better advantage in terms of LVDS support channel when compared to a Cyclone® V device. Agilex™ 5 receiver can support additional modes, such as soft-CDR and DPA FIFO, that Cyclone® V devices do not support.

As for VCCIO_PIO support, both devices are mutually different from each other. Agilex™ 5 device only supports J-factor 4 and 8, and Cyclone® V device supports J-factors from 4 to 10. In terms of supported I/O standards, Agilex™ 5 device supports true differential signaling and SLVS-400 I/O standards. However, a Cyclone® V device supports LVDS, SLVS (only receiver), mini-LVDS, RSDS, emulated LVDS, emulated mini-LVDS, and emulated RSDS at the transmitter.

Each Agilex™ 5 HSIO bank contains its own PLL. The PLL drives all receiver and transmitter channels in the same bank. However, the bank PLL cannot drive receiver and transmitter channels in another HSIO bank. You must use the dedicated clock pins to drive the LVDS PLLs. For a Cyclone® V device, each PLL drives all LVDS channels at I/O banks located at the same edge of the chip.

There are differences between true differential signaling in Agilex™ 5 device and other interfaces (such as LVDS, RSDS, and mini-LVDS) in terms of the VICM and VID. For optimum performance, ensure that your design meets the VICM and VID requirements of the receiver buffer in the Agilex™ 5 device.

Due to the differences between Cyclone® V and Agilex™ 5 devices, you must identify if the Agilex™ 5 device supports the LVDS SERDES feature when planning to migrate from Cyclone® V devices. For more information, refer to the LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs and Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration.

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