Follow these steps to upgrade the IP core:

1. Click Launch IP Upgrade Tool.
   Figure 13.  Launch IP Upgrade Tool Bar in the Quartus® Prime Pro Edition Software

   

   In the Upgrade IP Components dialog, the Auto Upgrade button is greyed out, which means that you must upgrade the Platform Designer system manually.

   Figure 14.  Upgrade IP Components Dialog

   
   Note: You have two options for upgrading IPs. Depending on the severity of the IP upgrade needed, you can perform an automatic upgrade in the Upgrade IP Components dialog or a manual upgrade using the Platform Designer. Elaborations are presented if a manual upgrade is needed.
2. Click the Upgrade in Editor button to perform a manual upgrade.

   You are prompted to convert the system to Pro format, with a warning that it cannot be used in other editions of the Quartus® Prime software.

3. Click OK.
   Figure 15. Warning Message

   
   Note: Click Project > Archive Project to save a copy of your original project before making modifications for migration.

   Observe the conversion results once the Platform Designer in Quartus Pro Conversion Results dialog appears. Updated IP Variants are automatically added to the Quartus® Prime project.

   Figure 16.  Platform Designer in Quartus Pro Conversion Results Dialog

   
4. Click OK.
   Note: There may be a dialog displaying ‘What’s New!’ in the Platform Designer. You can explore the information about new features and close the window.
5. Close the Open System Completed dialog.

   The Platform Designer GUI shows that all IP cores have been automatically upgraded to the latest version. To further confirm this, click System > Upgrade IP Cores. No IP cores are listed, as everything has been updated to the latest version.

   Figure 17. Upgrade IP Cores Dialog

   
6. Upgrade IP Cores manually in the Platform Designer as shown in the following sections.

Upgrading PLL Intel® FPGA IP

In the Platform Designer System View, observe that the pll IP core is highlighted in red.

Figure 18. pll IP core in the System View

The IP component is missing its details. This is because the PLL Intel® FPGA IP used in the Cyclone® V design is supported only by certain device families in the Quartus® Prime Standard Edition. This IP core is unavailable in the Quartus® Prime Pro Edition edition. In the right-hand Parameters tab, the IP is shown as a Missing Module.

Figure 19. Missing Module Dialog

The closest equivalent for the IP core in the Quartus® Prime Pro Edition is the IOPLL Intel® FPGA IP. For other IP cores showing Missing Module, refer to IP Comparison Between Cyclone V and Agilex 5 Devices for the IP core replacements in the Quartus® Prime Pro Edition software. You can also create a custom IP using the Quartus® Prime Standard Edition User Guide: Platform Designer .

To replace the missing module with the IOPLL Intel® FPGA IP, perform the following steps:

1. Remove the component from the system by right-clicking on pll and click Remove in its context-sensitive menu.
2. In the IP Catalog > IP tab, search iopll.
   Figure 20. Searching iopll in the IP Catalog

   
3. Double-click the IP core under Basic Function > Clocks; PLLs and Resets > PLL to instantiate the IP. The IOPLL Intel® FPGA IP dialog appears.
4. Parametrize the IP.
   1. Set the Reference Clock Frequency to 50 MHz.
   2. Uncheck the Enable locked output port option.
   3. Set outclk0’s Desired Frequency to 125 MHz.
   4. Leave the remaining fields with their default values.
   5. In the HDL entity name field, name the IP component as new_pll.
      Figure 21. Parameterization of the IOPLL Intel® FPGA IP

      
   6. Click Finish.
   7. Shift the IP to be under reset IP by selecting the component and clicking the Move Up button.
   Figure 22. new_pll IP in the System View

   

Nios® II Processor

Altera® has discontinued the support for the Nios® II Processor in March 2024 (see PDN 2312). You must upgrade any Nios® II usage to the Nios® V processor variants.

Figure 23. Missing Nios® V Module in the Parameters View

Figure 24. Missing Nios® V Module in the System View

Replace the Nios® II Processor in this design with the Nios® V/m Microcontroller Intel® FPGA IP. For more information about the Nios® V processor, refer to the Nios® V Embedded Processor Design Handbook .

Remove the IP core and replace it using the following steps:

1. Remove the nios2 component by right-clicking on it and selecting Remove in its context-sensitive menu.
2. Click Yes for the delete IP variant file warning message.
   Figure 25. Delete IP Variant File Warning Message

   
3. From the IP Catalog, search nios.
4. Double-click Nios® V/m Microcontroller Intel® FPGA IP under Processors and Peripherals > Embedded Processors.
   Figure 26. Searching nios in the IP Catalog

   
5. Instantiate the IP using the default configurations.
6. Rename the HDL entity name to niosv.
   Figure 27. Parameterization of the Nios® V/m Microcontroller Intel® FPGA IP

   
7. Click Finish.
8. Using the Move Up button, move niosv to be under the new_pll component.

On-Chip Memory (RAM or ROM) Intel® FPGA IP

When you select the ocm IP component (On-Chip Memory (RAM or ROM) Intel® FPGA IP) in the System View, you can observe warning messages in the Parameters > Parameterization Messages pane, which suggests using the On-Chip Memory (RAM or ROM) II Intel® FPGA IP as a replacement because the previous IP is not supported by Agilex™ 5 devices.

Figure 28. Parameterization of the On-Chip Memory (RAM or ROM) Intel® FPGA IP

To remove the IP core and replace it, perform these steps:

1. Remove the component by right-clicking on the ocm IP component and choosing Remove from its context-sensitive menu.
2. Click Yes to the warning message about the IP deletion and that the IP variant file deletions cannot be undone.
3. From the IP Catalog, search onchip.
4. Double-click On-Chip Memory II (RAM or ROM) Intel® FPGA IP under Basic Functions > On Chip Memory.
   Figure 29. Searching onchip in the IP Catalog

   
5. Parametrize the IP.
   1. Set Total Memory Size to 64000 bytes.
   2. Rename the HDL entity name field to new_ocm.
6. Click Finish.

Agilex Reset Release Intel® FPGA IP

Intel® requires that you use the Reset Release Intel® FPGA IP to hold your design in reset until the configuration is complete. For more information about this IP core, refer to the Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs .

To add the IP core, follow these steps:

1. From the IP Catalog, search reset.
2. Double-click Agilex Reset Release Intel® FPGA IP under Basic Functions > Configuration and Programming to instantiate the IP.
   Figure 30. Searching reset in the IP Catalog

   
3. Set Type of reset output port to Reset Interface.
4. Rename the HDL entity name to resetrelease.
5. Click Finish.