Intel® Simics® Simulator for Intel® FPGAs: User Guide

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ID 784383
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. About This Document 2. Intel® Simics® Simulator and Virtual Platforms 3. Intel® Simics® Simulator for Intel® FPGAs Device Portfolio 4. Installing the Intel® Simics® Simulator for Intel® FPGAs 5. Getting Started with Intel® Simics® Simulator 6. Debugging Target Software 7. Networking with the Simulated Target System 8. Intel® Simics® Scripting 9. Software Debug Examples with Intel® Simics® Simulator 10. Document Revision History for Intel® Simics® Simulator for Intel FPGAs User Guide A. Intel® Simics® Simulator Command Reference
1. About This Document x
1.1. Documentation Conventions for Examples 1.2. Terminology 1.3. List of Acronyms
2. Intel® Simics® Simulator and Virtual Platforms x
2.1. Device Model and Virtual Platforms 2.2. Intel® Simics® Simulator 2.3. Intel® Simics® Simulator Architecture
2.2. Intel® Simics® Simulator x
2.2.1. Intel® Simics® Simulator for Intel FPGAs Capabilities
4. Installing the Intel® Simics® Simulator for Intel® FPGAs x
4.1. Installing the Intel® Simics® Simulator for Intel® FPGAs on Linux* Systems 4.2. Installing the Intel® Simics® Simulator for Intel® FPGAs on Microsoft Windows* Systems 4.3. Installing Ashling* RiscFree* IDE for Intel® FPGAs 4.4. Intel® Simics® Simulator for Intel® FPGAs Support
5. Getting Started with Intel® Simics® Simulator x
5.1. Simulation Set Up 5.2. Starting the Simulation 5.3. Intel® Simics® Simulator Command-Line Interface (CLI) 5.4. Hardware Inspection 5.5. Intel® Simics® Simulator Timing
5.1. Simulation Set Up x
5.1.1. Initializing an Intel® Simics® Project and Deploying a Virtual Platform 5.1.2. Understanding Target Scripts
5.2. Starting the Simulation x
5.2.1. Starting a Simulation from a Command Prompt 5.2.2. Starting a Simulation with Ashling* RiscFree* IDE
5.3. Intel® Simics® Simulator Command-Line Interface (CLI) x
5.3.1. Version of the Intel® Simics® Simulator for Intel FPGAs Software 5.3.2. Simulation Run Control from CLI 5.3.3. Intel® Simics® Simulator Command Scope 5.3.4. Intel® Simics® Simulator CLI Variables and Operations 5.3.5. Intel® Simics® Simulator CLI Command Completion and Command History 5.3.6. Intel® Simics® Command-Line Interface Help 5.3.7. Capture of CLI Session to a File 5.3.8. Intel® Simics® Simulator File Location and Intel® Simics® Search Path
5.4. Hardware Inspection x
5.4.1. Listing Objects in the Target System 5.4.2. Processor (CPU) Inspection 5.4.3. Device Inspection 5.4.4. Memory Mapping and Memory Inspection 5.4.5. Logging
5.4.2. Processor (CPU) Inspection x
5.4.2.1. Listing Processors 5.4.2.2. Inspect Processor Registers
5.4.3. Device Inspection x
5.4.3.1. Retrieve List of Devices 5.4.3.2. Inspecting Device Registers
5.4.4. Memory Mapping and Memory Inspection x
5.4.4.1. Memory Mapping Inspection 5.4.4.2. Memory Inspection
5.4.5. Logging x
5.4.5.1. Breakpoints on CLI Log Messages
5.5. Intel® Simics® Simulator Timing x
5.5.1. CPU Frequency 5.5.2. CPU Cycles and Steps 5.5.3. Events 5.5.4. Enable Real Time
6. Debugging Target Software x
6.1. Intel® Simics® Debugger and Debug Context 6.2. Capturing Serial Console Output 6.3. Breakpoints 6.4. Debugging Target Software with Symbol Files 6.5. Debugging Target Software with Ashling* RiscFree* Debugger 6.6. Capturing CPU Instruction Execution Trace
6.3. Breakpoints x
6.3.1. Memory Breakpoints 6.3.2. Temporal Breakpoints 6.3.3. CPU Control Register Breakpoints 6.3.4. Hardware Access Breakpoints 6.3.5. CPU Register Breakpoints 6.3.6. Tracing Breakpoints 6.3.7. Text Console Activity Breakpoints
6.4. Debugging Target Software with Symbol Files x
6.4.1. Loading Symbol Files in a Simulation
6.5. Debugging Target Software with Ashling* RiscFree* Debugger x
6.5.1. Remote Debugging with RiscFree* IDE
6.5.1. Remote Debugging with RiscFree* IDE x
6.5.1.1. Remote Debugging With Intel® Simics® Simulation and RiscFree* IDE on the Same System 6.5.1.2. Remote Debugging With Intel® Simics® Simulation and RiscFree* IDE on Different Systems 6.5.1.3. Remote Access to the Target System Serial Console
7. Networking with the Simulated Target System x
7.1. Network Simulation and Service Node 7.2. Connectivity Between Host PC and Target System
7.2. Connectivity Between Host PC and Target System x
7.2.1. Port Forwarding 7.2.2. Transferring Files Between Host PC and Target System 7.2.3. Accessing Target System from Host PC Through HTTP 7.2.4. Networking Commands Reference Table
7.2.1. Port Forwarding x
7.2.1.1. Incoming Port Forwarding 7.2.1.2. Outgoing Port Forwarding
7.2.1.1. Incoming Port Forwarding x
7.2.1.1.1. Example of an SSH Connection with Incoming Port Forwarding
7.2.1.2. Outgoing Port Forwarding x
7.2.1.2.1. Example of SSH Connection With Outgoing Port Forwarding 7.2.1.2.2. Example of SSH Connection via NAPT
7.2.2. Transferring Files Between Host PC and Target System x
7.2.2.1. Transferring Files with SCP service 7.2.2.2. Transferring Files with TFTP service
7.2.2.1. Transferring Files with SCP service x
7.2.2.1.1. Transferring Files With SCP Service via Forwarding Ports 7.2.2.1.2. Transferring Files with SCP from Target System to Host PC via NAPT
7.2.2.2. Transferring Files with TFTP service x
7.2.2.2.1. TFTP Using Forwarding Port 7.2.2.2.2. TFTP via NAPT 7.2.2.2.3. TFTP Using TFTP Server in Intel® Simics® Service Node
8. Intel® Simics® Scripting x
8.1. Scripts in CLI
8.1. Scripts in CLI x
8.1.1. Variables 8.1.2. Command Return Values 8.1.3. Control Flow Commands 8.1.4. Local Variables 8.1.5. Integer Conversion 8.1.6. Accessing Configuration Parameters 8.1.7. Error Handling in Scripts 8.1.8. Script Branches
8.1.8. Script Branches x
8.1.8.1. Script Branches Commands 8.1.8.2. Variables in Script Branches 8.1.8.3. Branch Synchronization 8.1.8.4. Canceling Script Branches 8.1.8.5. Script Branches Restrictions
9. Software Debug Examples with Intel® Simics® Simulator x
9.1. Debugging Linux* User-Mode Application
9.1. Debugging Linux* User-Mode Application x
9.1.1. Debugging a Linux Application with GDB 9.1.2. Debugging a Linux Application with RiscFree* IDE
9.1.1. Debugging a Linux Application with GDB x
9.1.1.1. Debugging with GDB Debug from Host PC Using Forwarding Ports 9.1.1.2. Debugging with GDB from Host PC with Intel® Simics® Simulator GDB Server
1. About This Document
2. Intel® Simics® Simulator and Virtual Platforms
3. Intel® Simics® Simulator for Intel® FPGAs Device Portfolio
4. Installing the Intel® Simics® Simulator for Intel® FPGAs
5. Getting Started with Intel® Simics® Simulator
6. Debugging Target Software
7. Networking with the Simulated Target System
8. Intel® Simics® Scripting
9. Software Debug Examples with Intel® Simics® Simulator
10. Document Revision History for Intel® Simics® Simulator for Intel FPGAs User Guide
A. Intel® Simics® Simulator Command Reference

6.3.6. Tracing Breakpoints

Tracing is a way to observe what is going on during the simulation. The Intel® Simics® simulator breakpoint manager includes tracing functionality for several types of events. This means that messages (in fact, Intel® Simics® simulator log messages) are printed when an event of the specified occurs. Such a sequence of messages is what is here is known as a trace. Next are shown some examples on how the trace functionality can be used. 

#Intel Simics simulator CLI

simics> bp.control_register.trace -all  
1
simics> bp.list
-------------------------------------------------------------------------
ID  Description                Enabled  Oneshot  Ignore Count   Hit Count
-------------------------------------------------------------------------
1   system...core[0] break     true    false           0           0
    on R/W of any register
-------------------------------------------------------------------------

simics> r 100
Processor system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0] is disabled - may take a long time to finish.
[bp.control_register trace] [trace:1] system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0] read of currentel
[bp.control_register trace] [trace:1] system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0] read of scr_el3
[bp.control_register trace] [trace:1] system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0] scr_el3 <- 0xf
[bp.control_register trace] [trace:1] system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0] cptr_el3 <- 0x0
[bp.control_register trace] [trace:1] system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0] read of currentel
[bp.control_register trace] [trace:1] system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0] cntfrq_el0 <- 0x17d78400
[bp.control_register trace] [trace:1] system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0] read of midr_el1
[bp.control_register trace] [trace:1] system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0] read of midr_el1

simics> bp.delete -all

simics> bp.memory.trace address = 0x0 length = 0x1000 -r

simics> bp.list
----------------------------------------------------------------------------
ID  Description                   Enabled  Oneshot  Ignore Count   Hit Count
----------------------------------------------------------------------------
2    system.cell_context          true     false        0             0
     break matching (addr=0x0,
     len=4096, access=r)
----------------------------------------------------------------------------

simics> r
[bp.memory trace] [trace:1] system.cell_context 'r' access to v:0x138 len=8
[bp.memory trace] [trace:1] system.cell_context 'r' access to v:0x554 len=4
[bp.memory trace] [trace:1] system.cell_context 'r' access to v:0x558 len=8
[bp.memory trace] [trace:1] system.cell_context 'r' access to v:0x560 len=8
[bp.memory trace] [trace:1] system.cell_context 'r' access to v:0x568 len=8
[bp.memory trace] [trace:1] system.cell_context 'r' access to v:0x570 len=8

In the above example, the following actions are being executed:

  • A trace breakpoint is being configured to detect any change in any of the CPU control registers. The core can be selected using the psel command. In this case, the current CPU selected was core0. You can see that this breakpoint trace received the ID 1, and this can be seen in the list of breakpoints using the bp.list command.
  • The trace output are log messages and can be controlled with the log-setup command. For example, each message can be prepended with a time stamp, indicating the processor, program counter and the cycle count at the point where the event occurred.
  • The simulation is run for 100 steps. Here, you can see that some control registers have been accessed and some trace messages have been printed in the Intel® Simics® simulator CLI.
  • All the breakpoints are deleted as preparation of the setup of the next trace breakpoint.
  • A new trace breakpoint is being configured to report a message on any read access to address range 0x0000-0x1000. This gets an ID = 2, which is observed using the bp.list command.
  • The simulation is run again, and the target software is commanded to do a memory read to address 0x000. After this, the new trace messages are displayed in the Intel® Simics® simulator CLI.

Several other types of events can also be traced, such as target console string output and hits at specific source code lines. The trace over source code lines is described later in this document as this requires using a symbol file to provide information to the debugger about the source code.

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