Visible to Intel only — GUID: glf1698454253824
Ixiasoft
Visible to Intel only — GUID: glf1698454253824
Ixiasoft
6.6. Capturing CPU Instruction Execution Trace
To achieve this, you can use the new-tracer-tool command from the Intel® Simics® CLI to create a tracer. If you want to save the trace into a file, this command receives the file name where the tracer logs the information as a parameter. You can also indicate if the trace file must include data memory information, exceptions trace, and if you want to capture the virtual, physical, or linear address of the instruction executed.
The following capture shows an example of the use of this command to generate a CPU instructions trace file. Here, the trace file created is named instruction_trace.txt, in which instructions, exceptions, and physical and virtual addresses are logged. The tracer name is tracer1, and the tracer gets connected to all CPUs in the configuration. The log file is created under the project directory by default.
#Intel Simics simulator CLI simics> new-tracer-tool "tracer1" instruction_trace.txt -connect-all -trace-instructions -trace-exceptions -print-virtual-address -print-physical-address Created tracer1 (connected to 4 processors) simics> !ls instruction_trace.txt instruction_trace.txt simics> run 500 cycles simics> !more instruction_trace.txt :::::::::::::: instruction_trace.txt :::::::::::::: inst: [ 1] core[0] <v:0x0000000000000000> <p:0x0000000000> 0a 00 00 14 b 0x28 inst: [ 2] core[0] <v:0x0000000000000028> <p:0x0000000028> 34 00 00 14 b 0xf8 inst: [ 3] core[0] <v:0x00000000000000f8> <p:0x00000000f8> cd ff ff 17 b 0x2c inst: [ 4] core[0] <v:0x000000000000002c> <p:0x000000002c> 41 42 38 d5 mrs x1, currentel inst: [ 5] core[0] <v:0x0000000000000030> <p:0x0000000030> 3f 20 00 f1 cmp x1, #0x8 inst: [ 6] core[0] <v:0x0000000000000034> <p:0x0000000034> 6c 00 00 54 b.gt 0x40 inst: [ 7] core[0] <v:0x0000000000000040> <p:0x0000000040> 00 11 3e d5 mrs x0, scr_el3 inst: [ 8] core[0] <v:0x0000000000000044> <p:0x0000000044> 00 0c 40 b2 orr x0, x0, #0xf inst: [ 9] core[0] <v:0x0000000000000048> <p:0x0000000048> 00 11 1e d5 msr scr_el3, x0 inst: [ 10] core[0] <v:0x000000000000004c> <p:0x000000004c> 5f 11 1e d5 msr cptr_el3, xzr inst: [ 11] core[0] <v:0x0000000000000050> <p:0x0000000050> 0a 00 00 14 b 0x78 inst: [ 12] core[0] <v:0x0000000000000078> <p:0x0000000078> ff 44 03 d5 msr daifclr, #4