Intel® Simics® Simulator for Intel® FPGAs: User Guide

ID 784383
Date 7/08/2024
Public
Document Table of Contents

5.4.4.1. Memory Mapping Inspection

A memory space is a fundamental abstraction in the Intel® Simics® simulator providing support for generic 64-bit address spaces into which memory and devices can be mapped. More concretely, a memory space takes a stream of transactions to an address space and distributes them to devices mapped into the address space in a highly efficient manner while optionally providing address translations, byte swapping, and breakpoint support. Memory space objects can be cascaded to form arbitrarily complex mappings and support dynamic reconfiguration and remapping at run time through attributes to support the modeling of buses with dynamic addressing.

In the previous section, the use of devs command was described. As part of the output of this command, the memory space to which each device belongs is presented in the space column in the table.

Similarly, you can determine the devices that are mapping into a memory space. This can be done using the following commands:

 <memory_space>.map
<memory_space>.memory-map
The output for each one of these commands slightly differs but in both cases, the memory mapping is shown as follows:
# Intel Simics simulator CLI

simics> system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.map
---------------------------------------------------------------------------------
Base          Object                Fn  Offset  Length  Target  Prio Align Swap
---------------------------------------------------------------------------------
0x0         agilex_hps.ocram             0x0    0x80000           0   
0x10808000  ..sdmmc.bank.sdmmc_bank      0x0    0x1000            0
0x10810000  ..tsn0.bank.csr              0x0    0x4000            0
:
---------------------------------------------------------------------------------
Besides the two commands presented above, there are some other commands that can be executed from a memory space. These commands allow to add or remove a mapping, read and write from/to a memory location under the memory space among many other options:
# Intel Simics simulator CLI
simics> system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.  <double tab>
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.add-map
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.bp-break-memory
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.bp-run-until-memory
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.bp-trace-memory
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.bp-wait-for-memory
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.debug
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.del-map
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.examine-memory
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.get
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.get-string
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.info
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.load-binary
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.load-file
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.load-intel-hex
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.load-intel-obj
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.load-vmem
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.log-group
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.log-level
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.map
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.memory-map
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.read
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.read-string
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.save-file
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.save-intel-32-obj
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.save-intel-hex
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.save-intel-obj
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.save-vmem
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.set
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.set-string
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.status
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.wait-for-get
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.wait-for-read
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.wait-for-set
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.wait-for-write
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.write
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.write-string
system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.x

Another helpful command is the memory-map. This displays the physical memory map including translator for the current selected processor (information from another processor can be shown using the object command parameter).

# Intel Simics simulator CLI

simics> memory-map system.board.fpga.soc_inst.hps_subsys.agilex_hps.cpu_mem[0]
---------------------------------------------------------
Start       End            Object                 Offset
---------------------------------------------------------
0x00000   0x00fff   system…agilex_hps.ocram            
0x01000   0x01fff   system…agilex_hps.ocram       0x1000
0x02000   0x02fff   system…agilex_hps.ocram       0x2000
0x03000   0x03fff   system…agilex_hps.ocram       0x3000
:
---------------------------------------------------------

You can use the probe-adddress command to determine if there is a device associated with a specific address (i.e., if a device is mapped at that address) and if that device has any register mapped at that location. The following example shows this command identifying what is mapped at address 0x10D11000. In this example, this address corresponds to the stat register in the Reset Manager and can be seen in the following captured output:

# Intel Simics simulator CLI
simics> probe-address 0x10D11000

Translating virtual address to physical: 0x10d11000 -> p:0x8000000010d11000
------------------------------------------------------------------                             
Target                                Offset                Notes
------------------------------------------------------------------
system..agilex_hps.cpu_mem[0]        0x8000000010d11000    
system...agilex_hps.bt               0x8000000010d11000       +
system...agilex_hps.phys_mem         0x0000000010d11000    
system...agilex_hps.rstmgr.bank.regs 0x0000000000000000 
------------------------------------------------------------------
'+' - Translator implementing 'translate' interface
Destination: system.board.fpga.soc_inst.hps_subsys.agilex_hps.rstmgr.bank.regs offset 0x0
Register:    STAT @ 0x0 (4 bytes) + 0