Intel® Simics® Simulator for Intel® FPGAs: User Guide

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ID 784383
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. About This Document 2. Intel® Simics® Simulator and Virtual Platforms 3. Intel® Simics® Simulator for Intel® FPGAs Device Portfolio 4. Installing the Intel® Simics® Simulator for Intel® FPGAs 5. Getting Started with Intel® Simics® Simulator 6. Debugging Target Software 7. Networking with the Simulated Target System 8. Intel® Simics® Scripting 9. Software Debug Examples with Intel® Simics® Simulator 10. Document Revision History for Intel® Simics® Simulator for Intel FPGAs User Guide A. Intel® Simics® Simulator Command Reference
1. About This Document x
1.1. Documentation Conventions for Examples 1.2. Terminology 1.3. List of Acronyms
2. Intel® Simics® Simulator and Virtual Platforms x
2.1. Device Model and Virtual Platforms 2.2. Intel® Simics® Simulator 2.3. Intel® Simics® Simulator Architecture
2.2. Intel® Simics® Simulator x
2.2.1. Intel® Simics® Simulator for Intel FPGAs Capabilities
4. Installing the Intel® Simics® Simulator for Intel® FPGAs x
4.1. Installing the Intel® Simics® Simulator for Intel® FPGAs on Linux* Systems 4.2. Installing the Intel® Simics® Simulator for Intel® FPGAs on Microsoft Windows* Systems 4.3. Installing Ashling* RiscFree* IDE for Intel® FPGAs 4.4. Intel® Simics® Simulator for Intel® FPGAs Support
5. Getting Started with Intel® Simics® Simulator x
5.1. Simulation Set Up 5.2. Starting the Simulation 5.3. Intel® Simics® Simulator Command-Line Interface (CLI) 5.4. Hardware Inspection 5.5. Intel® Simics® Simulator Timing
5.1. Simulation Set Up x
5.1.1. Initializing an Intel® Simics® Project and Deploying a Virtual Platform 5.1.2. Understanding Target Scripts
5.2. Starting the Simulation x
5.2.1. Starting a Simulation from a Command Prompt 5.2.2. Starting a Simulation with Ashling* RiscFree* IDE
5.3. Intel® Simics® Simulator Command-Line Interface (CLI) x
5.3.1. Version of the Intel® Simics® Simulator for Intel FPGAs Software 5.3.2. Simulation Run Control from CLI 5.3.3. Intel® Simics® Simulator Command Scope 5.3.4. Intel® Simics® Simulator CLI Variables and Operations 5.3.5. Intel® Simics® Simulator CLI Command Completion and Command History 5.3.6. Intel® Simics® Command-Line Interface Help 5.3.7. Capture of CLI Session to a File 5.3.8. Intel® Simics® Simulator File Location and Intel® Simics® Search Path
5.4. Hardware Inspection x
5.4.1. Listing Objects in the Target System 5.4.2. Processor (CPU) Inspection 5.4.3. Device Inspection 5.4.4. Memory Mapping and Memory Inspection 5.4.5. Logging
5.4.2. Processor (CPU) Inspection x
5.4.2.1. Listing Processors 5.4.2.2. Inspect Processor Registers
5.4.3. Device Inspection x
5.4.3.1. Retrieve List of Devices 5.4.3.2. Inspecting Device Registers
5.4.4. Memory Mapping and Memory Inspection x
5.4.4.1. Memory Mapping Inspection 5.4.4.2. Memory Inspection
5.4.5. Logging x
5.4.5.1. Breakpoints on CLI Log Messages
5.5. Intel® Simics® Simulator Timing x
5.5.1. CPU Frequency 5.5.2. CPU Cycles and Steps 5.5.3. Events 5.5.4. Enable Real Time
6. Debugging Target Software x
6.1. Intel® Simics® Debugger and Debug Context 6.2. Capturing Serial Console Output 6.3. Breakpoints 6.4. Debugging Target Software with Symbol Files 6.5. Debugging Target Software with Ashling* RiscFree* Debugger 6.6. Capturing CPU Instruction Execution Trace
6.3. Breakpoints x
6.3.1. Memory Breakpoints 6.3.2. Temporal Breakpoints 6.3.3. CPU Control Register Breakpoints 6.3.4. Hardware Access Breakpoints 6.3.5. CPU Register Breakpoints 6.3.6. Tracing Breakpoints 6.3.7. Text Console Activity Breakpoints
6.4. Debugging Target Software with Symbol Files x
6.4.1. Loading Symbol Files in a Simulation
6.5. Debugging Target Software with Ashling* RiscFree* Debugger x
6.5.1. Remote Debugging with RiscFree* IDE
6.5.1. Remote Debugging with RiscFree* IDE x
6.5.1.1. Remote Debugging With Intel® Simics® Simulation and RiscFree* IDE on the Same System 6.5.1.2. Remote Debugging With Intel® Simics® Simulation and RiscFree* IDE on Different Systems 6.5.1.3. Remote Access to the Target System Serial Console
7. Networking with the Simulated Target System x
7.1. Network Simulation and Service Node 7.2. Connectivity Between Host PC and Target System
7.2. Connectivity Between Host PC and Target System x
7.2.1. Port Forwarding 7.2.2. Transferring Files Between Host PC and Target System 7.2.3. Accessing Target System from Host PC Through HTTP 7.2.4. Networking Commands Reference Table
7.2.1. Port Forwarding x
7.2.1.1. Incoming Port Forwarding 7.2.1.2. Outgoing Port Forwarding
7.2.1.1. Incoming Port Forwarding x
7.2.1.1.1. Example of an SSH Connection with Incoming Port Forwarding
7.2.1.2. Outgoing Port Forwarding x
7.2.1.2.1. Example of SSH Connection With Outgoing Port Forwarding 7.2.1.2.2. Example of SSH Connection via NAPT
7.2.2. Transferring Files Between Host PC and Target System x
7.2.2.1. Transferring Files with SCP service 7.2.2.2. Transferring Files with TFTP service
7.2.2.1. Transferring Files with SCP service x
7.2.2.1.1. Transferring Files With SCP Service via Forwarding Ports 7.2.2.1.2. Transferring Files with SCP from Target System to Host PC via NAPT
7.2.2.2. Transferring Files with TFTP service x
7.2.2.2.1. TFTP Using Forwarding Port 7.2.2.2.2. TFTP via NAPT 7.2.2.2.3. TFTP Using TFTP Server in Intel® Simics® Service Node
8. Intel® Simics® Scripting x
8.1. Scripts in CLI
8.1. Scripts in CLI x
8.1.1. Variables 8.1.2. Command Return Values 8.1.3. Control Flow Commands 8.1.4. Local Variables 8.1.5. Integer Conversion 8.1.6. Accessing Configuration Parameters 8.1.7. Error Handling in Scripts 8.1.8. Script Branches
8.1.8. Script Branches x
8.1.8.1. Script Branches Commands 8.1.8.2. Variables in Script Branches 8.1.8.3. Branch Synchronization 8.1.8.4. Canceling Script Branches 8.1.8.5. Script Branches Restrictions
9. Software Debug Examples with Intel® Simics® Simulator x
9.1. Debugging Linux* User-Mode Application
9.1. Debugging Linux* User-Mode Application x
9.1.1. Debugging a Linux Application with GDB 9.1.2. Debugging a Linux Application with RiscFree* IDE
9.1.1. Debugging a Linux Application with GDB x
9.1.1.1. Debugging with GDB Debug from Host PC Using Forwarding Ports 9.1.1.2. Debugging with GDB from Host PC with Intel® Simics® Simulator GDB Server
1. About This Document
2. Intel® Simics® Simulator and Virtual Platforms
3. Intel® Simics® Simulator for Intel® FPGAs Device Portfolio
4. Installing the Intel® Simics® Simulator for Intel® FPGAs
5. Getting Started with Intel® Simics® Simulator
6. Debugging Target Software
7. Networking with the Simulated Target System
8. Intel® Simics® Scripting
9. Software Debug Examples with Intel® Simics® Simulator
10. Document Revision History for Intel® Simics® Simulator for Intel FPGAs User Guide
A. Intel® Simics® Simulator Command Reference

6.3.1. Memory Breakpoints

A memory breakpoint stops the simulation whenever a memory location in a specified address interval is accessed. The address interval can be of arbitrary length and the type of memory access can be specified as any combination of read, write, and execute. The command used to set a memory breakpoint is the following: 

bp.memory.break [object] address [length][-r][-w][-
x]["prefix"]["substr"]["pattern"]["mask"] [-once]
Table 19.  Memory Breakpoint Command Options
Argument Description
address

Access address that generates the breakpoint trigger. The address can be physical or virtual. To indicate the type of address:

  • p:<address> is for physical
  • v:<address> is for virtual.
length Range of memory that generates the breakpoint trigger starting from address argument.
-r -w -x Memory access type that generates the breakpoint trigger (read, write or execution). Any combination of these is allowed. By default, execution is selected if none of the arguments is provided.
“prefix" Break on instructions with this prefix. For example, a prefix "add" causes the breakpoint to only stop if the instruction begins with "add". The match is case insensitive.
“substr” Break on instructions with a certain syntax substring. For example, specifying a substring "r31" causes the breakpoint to stop only if the instruction contains the substring "r31". The match is case insensitive.
“pattern” “mask” Break on instructions with a certain bit-pattern. First, the mask is applied to the instruction and then, the result is compared with the pattern. For example, a pattern "0x0100" and mask "0x0101" causes the breakpoint to stop only on instructions whose first byte has the lowest bit set and the second not.
-once This causes the breakpoint to automatically be removed after it has triggered.

An example of the use of breakpoint on memory is shown in the next capture. In the example, the memory access to trigger the breakpoint must be done from the software target software. In this case, the u-boot prompt is used to generate memory accesses. 

#Intel Simics simulator CLI  

running> bp.memory.break -w p:0xffe00000 -once 
Breakpoint 1: break on 'w' access to 0xffe00000 in system…agilex_hps.cpu_mem[0] 

running> bp.memory.break -r p:0xffe00000  
Breakpoint 2: break on 'r' access to 0xffe00000 in system…agilex_hps.cpu_mem[0] 
Note: overlaps with breakpoint 1 

running> bp.list 
------------------------------------------------------------------------------
ID                  Description                   Enabled    Oneshot Hit count 
------------------------------------------------------------------------------
1  system...cpu_mem[0] .. addr=0xffe .. access=w) true       true      0          
2  system...cpu_mem[0] .. addr=0xffe .. access=r) true       false     0 
------------------------------------------------------------------------------

[agilex.hps.cpu_mem[0]] Breakpoint 2: agilex.hps.cpu_mem[0] 'r' access to p:0xffe00000 len=4 
simics> bp.list
------------------------------------------------------------------------------
ID                  Description                   Enabled    Oneshot Hit count 
------------------------------------------------------------------------------
1  system...cpu_mem[0] .. addr=0xffe .. access=w) true       true              
2  system...cpu_mem[0] .. addr=0xffe .. access=r) true       false      1 
------------------------------------------------------------------------------

simics> r 
[system…agilex_hps.cpu_mem[0]] Breakpoint 1: system…agilex_hps.cpu_mem[0] 
'w' access to p:0xffe00000 len=4 val=0xcafecafe 

simics> bp.list
------------------------------------------------------------------------------
ID  Description                                   Enabled    Oneshot Hit count 
------------------------------------------------------------------------------
2  system...cpu_mem[0] .. addr=0xffe .. access=r) true       false      2 
------------------------------------------------------------------------------

simics> bp.delete 2 
simics> bp.list
------------------------------------------------------------
ID  Description   Enabled  Oneshot  Ignore Count  Hit count
------------------------------------------------------------ 
------------------------------------------------------------

In the capture above, the following actions are done:

  • A breakpoint is being set at physical memory address 0xFFE00000 on write access. The –once flag is being set, meaning that once it triggers, it is deleted.
  • A second breakpoint is being set also at physical memory address 0xFFE00000 on read access. The breakpoints are listed and it shows the two breakpoints added. Both breakpoints show their hit count is 0.
  • In the target software, a read operation on the 0xFFE00000 address is being generated. This makes the second breakpoint to trigger, and the simulation gets stopped. The breakpoints are listed, and you notice that the hit counter for the second breakpoint is now 1.
  • The simulation is run again and this time, a write operation to the 0xFFE00000 is being generated in the target software. This makes the first breakpoint to trigger, and the simulation gets stopped. The breakpoints are listed, and this time, the breakpoint 1 is no longer in the list as this was removed due to the –once flag.
  • The simulation is run again. In the target software, a new read operation on the 0xFFE00000 address is being generated. This makes the second breakpoint to trigger, and the simulation gets stopped. The breakpoints are listed, and you notice that the hit counter for the second breakpoint is now 2.
  • You delete second breakpoint and when breakpoints get listed, this does not show any breakpoint this time.
Note: The memory breakpoint can also be set using directly the memory space name. As an example of this, the following commands also create breakpoints on memory accesses: 
#Intel Simics simulator CLI 

simics> system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem.bp-break-memory 0xffe00000 -w
Breakpoint 3: break on 'w' access to 0xffe00000 in agilex.hps.cpu_mem[0]

simics> system.board.fpga.soc_inst.hps_subsys.agilex_hps.cpu_mem[0].bp-break-memory 0xffe00000 -r 
Breakpoint 4: break on 'r' access to 0xffe00000 in system.board.fpga.soc_inst.hps_subsys.agilex_hps.phys_mem
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