External Memory Interface Handbook Volume 1: Intel® FPGA Memory Solution Introduction and Design Flow: For UniPHY-based Device Families

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ID 710283
Date 3/06/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to this Handbook 2. Recommended Design Flow 3. Selecting Your Memory 4. Selecting Your FPGA Device
1. Introduction to this Handbook x
1.1. Introduction to Memory Solutions 1.2. Protocol Support Matrix 1.3. Document Revision History
2. Recommended Design Flow x
2.1. Getting Started With External Memory Interfaces 2.2. Document Revision History
2.1. Getting Started With External Memory Interfaces x
2.1.1. Selecting Your External Memory Device 2.1.2. Selecting Your FPGA 2.1.3. Planning Your Pin Requirements 2.1.4. Planning Your FPGA Resources 2.1.5. Determining Your Board Layout 2.1.6. Specifying Parameters for Your External Memory Interface 2.1.7. Performing Functional Simulation 2.1.8. Adding Design Constraints 2.1.9. Compiling Your Design and Verifying Timing 2.1.10. Verifying and Debugging External Memory Interface Operation
3. Selecting Your Memory x
3.1. DDR SDRAM Features 3.2. DDR2 SDRAM Features 3.3. DDR3 SDRAM Features 3.4. QDR, QDR II, and QDR II+ SRAM Features 3.5. RLDRAM II and RLDRAM 3 Features 3.6. LPDDR2 Features 3.7. Memory Selection 3.8. Example of High-Speed Memory in Embedded Processor 3.9. Example of High-Speed Memory in Telecom 3.10. Document Revision History
4. Selecting Your FPGA Device x
4.1. Memory Standards 4.2. I/O Interfaces 4.3. Wraparound Interfaces 4.4. Read and Write Leveling 4.5. Dynamic OCT 4.6. Device Settings Selection 4.7. Document Revision History
4.6. Device Settings Selection x
4.6.1. Device Speed Grade 4.6.2. Device Operating Temperature 4.6.3. Device Package Size 4.6.4. Device Density and I/O Pin Counts
1. Introduction to this Handbook
2. Recommended Design Flow
3. Selecting Your Memory
4. Selecting Your FPGA Device

2.2. Document Revision History

Date Version Changes
May 2017 2017.05.08 Rebranded as Intel.
October 2016 2016.10.31 Maintenance release.
May 2016 2016.05.02 Maintenance release.
November 2015 2015.11.02 Changed instances of Quartus II to Quartus Prime.
May 2015 2015.05.04 Maintenance release.
December 2014 2014.12.15
  • Revised the External Memory Interfaces Design Flowchart.
  • Removed the Design Checklist and added Getting Started With External Memory Interfaces, and associated subtopics.
August 2014 2014.08.15 Removed MegaWizard Plug-In Manager flow and added IP Catalog Flow to External Memory Interfaces Design Flowchart.
December 2013 2013.12.16
  • Removed references to ALTMEMPHY.
  • Removed references to SOPC Builder.
  • Removed ALTMEMPHY-related step from design checklist.
June 2012 2013.12.02
  • Removed overlapping information.
  • Added Feedback icon.
November 2011 2.1 Updated the design flow and the design checklist.
July 2010 2.0 Updated for 10.0 release.
January 2010 1.1
  • Improved description for Implementing Altera Memory Interface IP chapter.
  • Added timing simulation to flow chart and to design checklist.
November 2009 1.0 Initial release.
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