External Memory Interface Handbook Volume 1: Intel® FPGA Memory Solution Introduction and Design Flow: For UniPHY-based Device Families

ID 710283
Date 3/06/2023
Public
Document Table of Contents

2.1.8. Adding Design Constraints

Design constraints establish the timing characteristics of your IP and the physical locations of I/O and routing resources.
  1. Add timing constraints.
  2. Add pin assignments.
  3. Add pin location assignments.
  4. Ensure that the example top-level file or your top-level logic is set as top-level entity.
  5. Adjust optimization techniques, to ensure the remaining unconstrained paths are routed with the highest speed and efficiency, as follows:
    1. In the Intel® Quartus® Prime software, click Assignments > Settings.
    2. In the Settings dialog box, select the Compiler Settings category.
    3. In the Compiler Settings dialog box, click Advanced Settings (Synthesis) and set the Optimization Technique value to Speed.
    4. In the Compiler Settings dialog box, click Advanced Settings (Fitter) and set Optimize hold timing to All Paths. Turn on Optimize multi-corner timing. Set Fitter Effort to Standard Fit.