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2.1.1. Selecting Your External Memory Device
2.1.2. Selecting Your FPGA
2.1.3. Planning Your Pin Requirements
2.1.4. Planning Your FPGA Resources
2.1.5. Determining Your Board Layout
2.1.6. Specifying Parameters for Your External Memory Interface
2.1.7. Performing Functional Simulation
2.1.8. Adding Design Constraints
2.1.9. Compiling Your Design and Verifying Timing
2.1.10. Verifying and Debugging External Memory Interface Operation
3.1. DDR SDRAM Features
3.2. DDR2 SDRAM Features
3.3. DDR3 SDRAM Features
3.4. QDR, QDR II, and QDR II+ SRAM Features
3.5. RLDRAM II and RLDRAM 3 Features
3.6. LPDDR2 Features
3.7. Memory Selection
3.8. Example of High-Speed Memory in Embedded Processor
3.9. Example of High-Speed Memory in Telecom
3.10. Document Revision History
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2.1.8. Adding Design Constraints
Design constraints establish the timing characteristics of your IP and the physical locations of I/O and routing resources.
- Add timing constraints.
- Add pin assignments.
- Add pin location assignments.
- Ensure that the example top-level file or your top-level logic is set as top-level entity.
- Adjust optimization techniques, to ensure the remaining unconstrained paths are routed with the highest speed and efficiency, as follows:
- In the Intel® Quartus® Prime software, click Assignments > Settings.
- In the Settings dialog box, select the Compiler Settings category.
- In the Compiler Settings dialog box, click Advanced Settings (Synthesis) and set the Optimization Technique value to Speed.
- In the Compiler Settings dialog box, click Advanced Settings (Fitter) and set Optimize hold timing to All Paths. Turn on Optimize multi-corner timing. Set Fitter Effort to Standard Fit.
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