External Memory Interface Handbook Volume 1: Intel® FPGA Memory Solution Introduction and Design Flow: For UniPHY-based Device Families

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ID 710283
Date 3/06/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to this Handbook 2. Recommended Design Flow 3. Selecting Your Memory 4. Selecting Your FPGA Device
1. Introduction to this Handbook x
1.1. Introduction to Memory Solutions 1.2. Protocol Support Matrix 1.3. Document Revision History
2. Recommended Design Flow x
2.1. Getting Started With External Memory Interfaces 2.2. Document Revision History
2.1. Getting Started With External Memory Interfaces x
The High-Level Tasks 2.1.1. Selecting Your External Memory Device 2.1.2. Selecting Your FPGA 2.1.3. Planning Your Pin Requirements 2.1.4. Planning Your FPGA Resources 2.1.5. Determining Your Board Layout 2.1.6. Specifying Parameters for Your External Memory Interface 2.1.7. Performing Functional Simulation 2.1.8. Adding Design Constraints 2.1.9. Compiling Your Design and Verifying Timing 2.1.10. Verifying and Debugging External Memory Interface Operation
3. Selecting Your Memory x
3.1. DDR SDRAM Features 3.2. DDR2 SDRAM Features 3.3. DDR3 SDRAM Features 3.4. QDR, QDR II, and QDR II+ SRAM Features 3.5. RLDRAM II and RLDRAM 3 Features 3.6. LPDDR2 Features 3.7. Memory Selection 3.8. Example of High-Speed Memory in Embedded Processor 3.9. Example of High-Speed Memory in Telecom 3.10. Document Revision History
4. Selecting Your FPGA Device x
4.1. Memory Standards 4.2. I/O Interfaces 4.3. Wraparound Interfaces 4.4. Read and Write Leveling 4.5. Dynamic OCT 4.6. Device Settings Selection 4.7. Document Revision History
4.6. Device Settings Selection x
4.6.1. Device Speed Grade 4.6.2. Device Operating Temperature 4.6.3. Device Package Size 4.6.4. Device Density and I/O Pin Counts
1. Introduction to this Handbook
2. Recommended Design Flow
3. Selecting Your Memory
4. Selecting Your FPGA Device

2.1. Getting Started With External Memory Interfaces

To create your external memory interface, you must complete several high-level tasks. This topic outlines the major tasks in the design flow, and provides links to detailed procedures for each task.

The High-Level Tasks

Refer to this section for a big-picture view of the overall design process, and for links to related information for each task.

  1. Selecting Your External Memory Device
    Different memory types excel in different areas. As a first step in planning your external memory interface, you must determine the memory type that best meets the requirements of your system.
  2. Selecting Your FPGA
    Different Intel® FPGA devices support different memory types; not all Intel® devices support all memory protocols and configurations. Before you start your design, you must select an Intel® device, which supports the memory standard and configurations you plan to use.
  3. Planning Your Pin Requirements
    Before you can specify parameters for your external memory interface, you must determine the pin requirements.
  4. Planning Your FPGA Resources
    Before you can specify parameters for your external memory interface, you must determine the FPGA resource requirements.
  5. Determining Your Board Layout
    Before you can specify parameters for your external memory interface, you must determine the necessary board-related settings for your IP.
  6. Specifying Parameters for Your External Memory Interface
    After you have determined all the necessary requirements, you can parameterize your external memory interface.
  7. Performing Functional Simulation
    Simulate your design to determine correct operation, timing closure, and overall latency.
  8. Adding Design Constraints
    Design constraints establish the timing characteristics of your IP and the physical locations of I/O and routing resources.
  9. Compiling Your Design and Verifying Timing
    When you compile your design, the Timing Analyzer generates timing reports for your design.
  10. Verifying and Debugging External Memory Interface Operation
    Operational problems can generally be attributed to one of the following: resource and planning problems, interface configuration problems, functional problems, signal integrity problems, or timing problems.
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