External Memory Interface Handbook Volume 1: Intel® FPGA Memory Solution Introduction and Design Flow: For UniPHY-based Device Families

ID 710283
Date 3/06/2023
Public
Document Table of Contents

2.1.9. Compiling Your Design and Verifying Timing

When you compile your design, the Timing Analyzer generates timing reports for your design.
  1. Compile your design by clicking Processing > Start Compilation.
    Memory timing scripts run automatically as part of Report DDR.
  2. Verify timing closure using all available models, and evaluate the timing reports generated by the Timing Analyzer.
    As required, adjust the constraints described in Adding Design Constraints to resolve timing or location issues.
  3. Iteratively recompile your IP and evaluate the timing results as necessary to achieve the required timing margins.