External Memory Interface Handbook Volume 1: Intel® FPGA Memory Solution Introduction and Design Flow: For UniPHY-based Device Families

ID 710283
Date 3/06/2023
Public
Document Table of Contents

4.4. Read and Write Leveling

The Arria V GZ, Stratix III, Stratix IV, and Stratix V I/O registers include read and write leveling circuitry to enable skew to be removed or applied to the interface on a DQS group basis. There is one leveling circuit located in each I/O subbank.
Note: UniPHY-based designs do not require read leveling circuitry during read leveling operation.

For more information about read and write leveling, refer to Leveling Circuitry section in the Functional Description - UniPHY chapter of the External Memory Interface Handbook.