External Memory Interface Handbook Volume 1: Intel® FPGA Memory Solution Introduction and Design Flow: For UniPHY-based Device Families

ID 710283
Date 3/06/2023
Public
Document Table of Contents

1.2. Protocol Support Matrix

The following table lists the device family, memory protocol, and IP architecture support for the UniPHY-based external memory interface IP in the current release of the Intel® Quartus® Prime Design Suite.
Figure 2. Protocol Support Matrix  (1)  (2)  (3) (4) (5)


Notes to Table:

  1. U= Supported by UniPHY-based IP.
  2. A = Supported by ALTMEMPHY-based IP. Refer to the External Memory Interface Handbook for the Quartus II software version 12.1 or earlier for information about ALTMEMPHY-based IP.
  3. = Not supported.
  4. The RTL-based sequencer is not available for QDR II or RLDRAM II interfaces targeting Arria® V devices.

For more information about the controllers with the Intel® UniPHY IP, refer to the Functional Descriptions section in Volume 3 of the External Memory Interface Handbook.

For more information on the Intel® MAX® 10 external memory interface IP, see Functional Description—MAX 10 EMIF IP.