Visible to Intel only — GUID: hco1416493266735
Ixiasoft
2.1.1. Selecting Your External Memory Device
2.1.2. Selecting Your FPGA
2.1.3. Planning Your Pin Requirements
2.1.4. Planning Your FPGA Resources
2.1.5. Determining Your Board Layout
2.1.6. Specifying Parameters for Your External Memory Interface
2.1.7. Performing Functional Simulation
2.1.8. Adding Design Constraints
2.1.9. Compiling Your Design and Verifying Timing
2.1.10. Verifying and Debugging External Memory Interface Operation
3.1. DDR SDRAM Features
3.2. DDR2 SDRAM Features
3.3. DDR3 SDRAM Features
3.4. QDR, QDR II, and QDR II+ SRAM Features
3.5. RLDRAM II and RLDRAM 3 Features
3.6. LPDDR2 Features
3.7. Memory Selection
3.8. Example of High-Speed Memory in Embedded Processor
3.9. Example of High-Speed Memory in Telecom
3.10. Document Revision History
Visible to Intel only — GUID: hco1416493266735
Ixiasoft
1.2. Protocol Support Matrix
The following table lists the device family, memory protocol, and IP architecture support for the UniPHY-based external memory interface IP in the current release of the Intel® Quartus® Prime Design Suite.
Figure 2. Protocol Support Matrix (1) (2) (3) (4) (5)
Notes to Table:
|
For more information about the controllers with the Intel® UniPHY IP, refer to the Functional Descriptions section in Volume 3 of the External Memory Interface Handbook.
For more information on the Intel® MAX® 10 external memory interface IP, see Functional Description—MAX 10 EMIF IP.