External Memory Interface Handbook Volume 1: Intel® FPGA Memory Solution Introduction and Design Flow: For UniPHY-based Device Families

ID 710283
Date 3/06/2023
Public
Document Table of Contents

3.10. Document Revision History

Date Version Changes
March 2023 2023.03.06
  • Removed Intel® Arria® 10 and Intel® Stratix® 10 references.
  • Removed LPDDR3 Features topic.
May 2017 2017.05.08 Rebranded as Intel.
October 2016 2016.10.31 Maintenance release.
May 2016 2016.05.02 Moved chapter from Volume 2 to Volume 1.
November 2015 2015.11.01 Added LPDDR3 features.
May 2015 2015.05.04 Maintenance release.
December 2014 2014.12.15 Modified note 3 on Memory Selection Overview table.
August 2014 2014.08.15
  • Changed some values in the Bandwidth for 32 bits, Bandwidth at % Efficiency, Performance / Clock frequency, and Altera-supported data rate rows of the Memory Selection Overview table.
December 2013 2013.12.16 Removed references to Stratix II devices.
November 2012 6.0 Added RLDRAM 3 support.
June 2012 5.0
  • Added LPDDR2 support.
  • Added Feedback icon.
November 2011 4.0 Moved and reorganized “Selecting your Memory” section to Volume 2: Design Guidelines.
June 2011 3.0 Added “Selecting Memory IP” chapter from Volume 2.
December 2010 2.1
  • Moved protocol-specific feature information to the memory interface user guides in Volume 3.
  • Updated maximum clock rate information for 10.1.
July 2010 2.0
  • Added specifications for DDR2 and DDR3 SDRAM Controllers with UniPHY.
  • Streamlined the specification tables.
  • Added reference to web-based Specification Estimator Tool.
January 2010 1.1 Updated DDR, DDR2, and DDR3 specifications.
November 2009 1.0 First published.