External Memory Interface Handbook Volume 1: Intel® FPGA Memory Solution Introduction and Design Flow: For UniPHY-based Device Families

ID 710283
Date 3/06/2023
Public
Document Table of Contents

2.1.6. Specifying Parameters for Your External Memory Interface

After you have determined all the necessary requirements, you can parameterize your external memory interface.
  1. In the parameter editor, set the parameters for the external memory IP for your target memory interface.
    • Refer to Specifying IP Core Parameters and Options for information about using the IP Catalog and parameter editor.
    • Refer to Implementing and Parameterizing Memory IP for detailed information about parameterizing external memory interface IP.
  2. Specify the correct parameters for each of the following:
    • Memory interface data rate, width, and configuration.
    • Necessary deratings for tIS, tIH, tDH, and tDS parameters, as appropriate.
    • Board skew parameters based on actual board simulation.
  3. Connect the local signals from the PHY and controller to your driver logic, and the memory interface signals from the PHY to the top-level pins.
    • It is important that you connect the local interface signals from the PHY or controller correctly to your own logic. If you do not connect these local interface signals, you might encounter problems with insufficient pins when you compile your design.
    • Logic that is not connected may be optimized away during compilation, resulting in problems later.
    • If you want to use your own custom memory controller with the Intel® PHY, you can refer to the example top-level file as an example for connecting your controller.