External Memory Interface Handbook Volume 1: Intel® FPGA Memory Solution Introduction and Design Flow: For UniPHY-based Device Families

ID 710283
Date 3/06/2023
Public
Document Table of Contents

4.2. I/O Interfaces

Ideally any interface should reside entirely in a single bank; however, interfaces that span across multiple adjacent banks or the entire side of a device are also fully supported.

Interfaces that span across sides (top and bottom, or left and right) and wraparound interfaces provide the same level of performance.

For information about the I/O interfaces supported for each device, and the locations of those I/O interfaces, refer to the I/O Features section in the appropriate device handbook.