External Memory Interface Handbook Volume 1: Intel® FPGA Memory Solution Introduction and Design Flow: For UniPHY-based Device Families

ID 710283
Date 3/06/2023
Public
Document Table of Contents

4.3. Wraparound Interfaces

For maximum performance, Intel® recommends that data groups for external memory interfaces should always be within the same side of a device, ideally reside within a single bank.

High-speed memory interfaces using top or bottom I/O bank versus left or right I/O bank have different timing characteristics, so the timing margins are also different. However, Intel® can support interfaces with wraparound data groups that wrap around a corner of the device between vertical and horizontal I/O banks at some speeds. Some devices support wraparound interfaces that run at the same speed as row or column interfaces.

Arria II GX devices can support wraparound interface across all sides of devices that are not used for transceivers. Other UniPHY-supported Intel® devices support only interfaces with data groups that wrap around a corner of the device.