External Memory Interface Handbook Volume 1: Intel® FPGA Memory Solution Introduction and Design Flow: For UniPHY-based Device Families

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ID 710283
Date 3/06/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to this Handbook 2. Recommended Design Flow 3. Selecting Your Memory 4. Selecting Your FPGA Device
1. Introduction to this Handbook x
1.1. Introduction to Memory Solutions 1.2. Protocol Support Matrix 1.3. Document Revision History
2. Recommended Design Flow x
2.1. Getting Started With External Memory Interfaces 2.2. Document Revision History
2.1. Getting Started With External Memory Interfaces x
2.1.1. Selecting Your External Memory Device 2.1.2. Selecting Your FPGA 2.1.3. Planning Your Pin Requirements 2.1.4. Planning Your FPGA Resources 2.1.5. Determining Your Board Layout 2.1.6. Specifying Parameters for Your External Memory Interface 2.1.7. Performing Functional Simulation 2.1.8. Adding Design Constraints 2.1.9. Compiling Your Design and Verifying Timing 2.1.10. Verifying and Debugging External Memory Interface Operation
3. Selecting Your Memory x
3.1. DDR SDRAM Features 3.2. DDR2 SDRAM Features 3.3. DDR3 SDRAM Features 3.4. QDR, QDR II, and QDR II+ SRAM Features 3.5. RLDRAM II and RLDRAM 3 Features 3.6. LPDDR2 Features 3.7. Memory Selection 3.8. Example of High-Speed Memory in Embedded Processor 3.9. Example of High-Speed Memory in Telecom 3.10. Document Revision History
4. Selecting Your FPGA Device x
4.1. Memory Standards 4.2. I/O Interfaces 4.3. Wraparound Interfaces 4.4. Read and Write Leveling 4.5. Dynamic OCT 4.6. Device Settings Selection 4.7. Document Revision History
4.6. Device Settings Selection x
4.6.1. Device Speed Grade 4.6.2. Device Operating Temperature 4.6.3. Device Package Size 4.6.4. Device Density and I/O Pin Counts
1. Introduction to this Handbook
2. Recommended Design Flow
3. Selecting Your Memory
4. Selecting Your FPGA Device

3.3. DDR3 SDRAM Features

DDR3 SDRAM is the third generation of SDRAM. DDR3 SDRAM is internally configured as an eight-bank DRAM and uses an 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined with an interface that transfers two data words per clock cycle at the I/O pins. A single read or write operation for DDR3 SDRAM consists of a single 8n-bit wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. DDR3 SDRAMs are available as components and modules, such as DIMMs, SODIMMs, RDIMMs, and LRDIMMs.

DDR3 SDRAM can conserve system power, increase system performance, achieve better maximum throughput, and improve signal integrity with fly-by topology and dynamic on-die termination.

Read and write operations to the DDR3 SDRAM are burst oriented. Operation begins with the registration of an active command, which is followed by a read or write command. The address bits registered coincident with the active command select the bank and row to be activated (BA0 to BA2 select the bank; A0 to A15 select the row). The address bits registered coincident with the read or write command select the starting column location for the burst operation, determine if the auto precharge command is to be issued (via A10), and select burst chop (BC) of 4 or burst length (BL) of 8 mode at runtime (via A12), if enabled in the mode register. Before normal operation, the DDR3 SDRAM must be powered up and initialized in a predefined manner.

Differential strobes DQS and DQSn are mandated for DDR3 SDRAM and are associated with a group of data pins, as is DQ for read and write operations. DQS, DQSn, and DQ ports are bidirectional. Address ports are shared for read and write operations.

Note: The DDR3 SDRAM high-performance controller II supports local interfaces running at full-rate, half-rate, and quarter-rate.

For more information, refer to the respective DDR, DDR2, and DDR3 SDRAM data sheets.

For more information about parameterizing the DDR2 and DDR3 SDRAM IP, refer to the Implementing and Parameterizing Memory IP chapter.

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