Visible to Intel only — GUID: sam1403482511865
Ixiasoft
Visible to Intel only — GUID: sam1403482511865
Ixiasoft
3.1.7.1. IOPLL IP Signal Interface with LVDS SERDES IP
From the IOPLL IP | To the LVDS SERDES IP Transmitter or Receiver | |
---|---|---|
Without CPA | With CPA | |
lvds_clk[0] (serial clock output signal)
The serial clock output can only drive ext_fclk on the LVDS SERDES IP transmitter and receiver. This clock cannot drive the core logic. |
ext_fclk (serial clock input to the transmitter or receiver) |
ext_fclk (serial clock input to the transmitter or receiver) |
loaden[0] (load enable output)
|
ext_loaden (load enable to the transmitter or receiver) This signal is not required for LVDS receiver in soft-CDR mode. |
ext_loaden (load enable to the transmitter or receiver) This signal is not required for LVDS receiver in soft-CDR mode. |
outclk4 (parallel clock output) This clock is not required if you turn on Use the CPA block for improved periphery-core timing. |
ext_coreclock (parallel core clock) |
— |
locked |
— | ext_pll_locked |
reset |
pll_areset (asynchronous PLL reset port) |
pll_areset (asynchronous PLL reset port) |
phout[7:0]
|
ext_vcoph[7:0] This signal is required only for LVDS receiver in DPA or soft-CDR mode. |
ext_vcoph[7:0] This signal is required for all transmitter or receiver modes. |