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1. Stratix® 10 High-Speed LVDS I/O Overview
2. Stratix® 10 High-Speed LVDS I/O Architecture and Features
3. Stratix 10 High-Speed LVDS I/O Design Considerations
4. Stratix® 10 High-Speed LVDS I/O Implementation Guides
5. LVDS SERDES Intel® FPGA IP References
6. Stratix® 10 High-Speed LVDS I/O User Guide Archives
7. Document Revision History for the Stratix® 10 High-Speed LVDS I/O User Guide
3.1. PLLs and Clocking for Stratix® 10 Devices
3.2. Source-Synchronous Timing Budget
3.3. Guideline: LVDS SERDES IP Core Instantiation
3.4. Guideline: LVDS SERDES Pin Pairs for Soft-CDR Mode
3.5. Guideline: LVDS Transmitters and Receivers in the Same I/O Bank
3.6. Guideline: LVDS SERDES Limitation for Stratix® 10 GX 400, SX 400, and TX 400
3.1.1. Clocking Differential Transmitters
3.1.2. Clocking Differential Receivers
3.1.3. Guideline: LVDS Reference Clock Source
3.1.4. Guideline: Use PLLs in Integer PLL Mode for LVDS
3.1.5. Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only
3.1.6. Guideline: Pin Placement for Differential Channels
3.1.7. LVDS Interface with External PLL Mode
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7. Document Revision History for the Stratix® 10 High-Speed LVDS I/O User Guide
Document Version | Quartus® Prime Version | Changes |
---|---|---|
2024.07.08 | 24.2 |
|
2022.11.30 | 22.1 | Updated the VCO Frequency information in Table: Example: Generating Output Clocks Using an IOPLL IP (Receiver in DPA or Soft-CDR Mode) |
2022.03.28 | 22.1 |
|
2021.07.13 | 21.2 | Updated the information about the receiver timing analysis in non-DPA mode. |
2021.05.28 | 21.1 | Updated the code to add to the .sdc file to specify the RCCS value. |
2021.03.29 | 21.1 | Added the IP release information. |
2020.11.13 | 20.3 |
|
2020.09.25 | 20.2 | Removed the Use clock-pin drive parameter from the LVDS SERDES IP core general settings. |
2020.07.14 | 20.2 | Updated the figure showing the I/O bank structure:
|
2020.01.03 | 19.4 |
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2019.07.10 | 19.2 | Corrected the clock connection to the register and rx_coreclock in the figure showing the connection for non-DPA or DPA receiver interface with the IOPLL IP core in external PLL mode. |
2019.05.02 | 19.1 |
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2019.02.26 | 18.1 | Updated the guidelines for the LVDS interface with external PLL mode:
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2019.01.14 | 18.1 | Removed statement that says that the programmable VOD value of "0" is not available for the LVDS I/O standard. |
2018.11.12 | 18.1 |
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2018.08.06 | 18.0 |
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Date | Version | Changes |
---|---|---|
November 2017 | 2017.11.06 |
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May 2017 | 2017.05.08 |
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February 2017 | 2017.02.13 | Removed the SF48 package from the Stratix® 10 TX 1650 and TX 2100 devices. |
October 2016 | 2016.10.31 | Initial release. |