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1. Stratix® 10 High-Speed LVDS I/O Overview
2. Stratix® 10 High-Speed LVDS I/O Architecture and Features
3. Stratix 10 High-Speed LVDS I/O Design Considerations
4. Stratix® 10 High-Speed LVDS I/O Implementation Guides
5. LVDS SERDES Intel® FPGA IP References
6. Stratix® 10 High-Speed LVDS I/O User Guide Archives
7. Document Revision History for the Stratix® 10 High-Speed LVDS I/O User Guide
3.1. PLLs and Clocking for Stratix® 10 Devices
3.2. Source-Synchronous Timing Budget
3.3. Guideline: LVDS SERDES IP Core Instantiation
3.4. Guideline: LVDS SERDES Pin Pairs for Soft-CDR Mode
3.5. Guideline: LVDS Transmitters and Receivers in the Same I/O Bank
3.6. Guideline: LVDS SERDES Limitation for Stratix® 10 GX 400, SX 400, and TX 400
3.1.1. Clocking Differential Transmitters
3.1.2. Clocking Differential Receivers
3.1.3. Guideline: LVDS Reference Clock Source
3.1.4. Guideline: Use PLLs in Integer PLL Mode for LVDS
3.1.5. Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only
3.1.6. Guideline: Pin Placement for Differential Channels
3.1.7. LVDS Interface with External PLL Mode
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4.1.4.5. Clock Phase Alignment
The CPA block helps improve timing closure between the periphery and the core. To use this feature, turn on the Use the CPA block for improved periphery-core timing option in the LVDS SERDES IP core parameter editor.
If you turn on the option, the LVDS SERDES IP core uses the CPA block to phase-align the core clock and the load enable clock.
SERDES Factor | Actual Core Clock Duty Cycle |
---|---|
3 | 66.6% |
4 | 50% |
5 | 40% |
6 | 33% |
7 | 40% |
8 | 50% |
9 | 40% |
10 | 40% |
The Use the CPA block for improved periphery-core timing option is available for any selectable SERDES factor under the following conditions:
- The IP core functional mode is TX, RX Non-DPA, or RX DPA-FIFO.
- The tx_outclock phase shift is a multiple of 180°.