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1. Stratix® 10 High-Speed LVDS I/O Overview
2. Stratix® 10 High-Speed LVDS I/O Architecture and Features
3. Stratix 10 High-Speed LVDS I/O Design Considerations
4. Stratix® 10 High-Speed LVDS I/O Implementation Guides
5. LVDS SERDES Intel® FPGA IP References
6. Stratix® 10 High-Speed LVDS I/O User Guide Archives
7. Document Revision History for the Stratix® 10 High-Speed LVDS I/O User Guide
3.1. PLLs and Clocking for Stratix® 10 Devices
3.2. Source-Synchronous Timing Budget
3.3. Guideline: LVDS SERDES IP Core Instantiation
3.4. Guideline: LVDS SERDES Pin Pairs for Soft-CDR Mode
3.5. Guideline: LVDS Transmitters and Receivers in the Same I/O Bank
3.6. Guideline: LVDS SERDES Limitation for Stratix® 10 GX 400, SX 400, and TX 400
3.1.1. Clocking Differential Transmitters
3.1.2. Clocking Differential Receivers
3.1.3. Guideline: LVDS Reference Clock Source
3.1.4. Guideline: Use PLLs in Integer PLL Mode for LVDS
3.1.5. Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only
3.1.6. Guideline: Pin Placement for Differential Channels
3.1.7. LVDS Interface with External PLL Mode
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4.5. IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices
The IP migration flow allows you to migrate the ALTLVDS_TX and ALTLVDS_RX IP cores of Arria® V, Cyclone® V, and Stratix® V devices to the LVDS SERDES Intel® FPGA IP of Stratix® 10 devices.
This IP migration flow configures the LVDS SERDES IP core to match the settings of the ALTLVDS_TX and ALTLVDS_RX IP cores, allowing you to regenerate the IP core.
Note: Some IP cores support the IP migration flow in specific modes only. If your IP core is in a mode that is not supported, you may need to run the IP Parameter Editor for the LVDS SERDES IP core and configure the IP core manually.