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1. Stratix® 10 High-Speed LVDS I/O Overview
2. Stratix® 10 High-Speed LVDS I/O Architecture and Features
3. Stratix 10 High-Speed LVDS I/O Design Considerations
4. Stratix® 10 High-Speed LVDS I/O Implementation Guides
5. LVDS SERDES Intel® FPGA IP References
6. Stratix® 10 High-Speed LVDS I/O User Guide Archives
7. Document Revision History for the Stratix® 10 High-Speed LVDS I/O User Guide
3.1. PLLs and Clocking for Stratix® 10 Devices
3.2. Source-Synchronous Timing Budget
3.3. Guideline: LVDS SERDES IP Core Instantiation
3.4. Guideline: LVDS SERDES Pin Pairs for Soft-CDR Mode
3.5. Guideline: LVDS Transmitters and Receivers in the Same I/O Bank
3.6. Guideline: LVDS SERDES Limitation for Stratix® 10 GX 400, SX 400, and TX 400
3.1.1. Clocking Differential Transmitters
3.1.2. Clocking Differential Receivers
3.1.3. Guideline: LVDS Reference Clock Source
3.1.4. Guideline: Use PLLs in Integer PLL Mode for LVDS
3.1.5. Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only
3.1.6. Guideline: Pin Placement for Differential Channels
3.1.7. LVDS Interface with External PLL Mode
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3.1.7.3. Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode
Figure 24. Non-DPA or DPA LVDS Receiver Interface with the IOPLL IP in External PLL Mode
Figure 25. Soft-CDR LVDS Receiver Interface with the IOPLL IP in External PLL Mode
Figure 26. LVDS Transmitter Interface with the IOPLL IP in External PLL ModeConnect the I/O PLL lvds_clk[1] and loaden[1] ports to the ext_fclk and ext_loaden ports of the LVDS transmitter.
The ext_coreclock port is automatically enabled in the LVDS SERDES IP in external PLL mode. The Quartus® Prime compiler outputs error messages if this port is not connected as shown in the preceding figures.