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1. Stratix® 10 High-Speed LVDS I/O Overview
2. Stratix® 10 High-Speed LVDS I/O Architecture and Features
3. Stratix 10 High-Speed LVDS I/O Design Considerations
4. Stratix® 10 High-Speed LVDS I/O Implementation Guides
5. LVDS SERDES Intel® FPGA IP References
6. Stratix® 10 High-Speed LVDS I/O User Guide Archives
7. Document Revision History for the Stratix® 10 High-Speed LVDS I/O User Guide
3.1. PLLs and Clocking for Stratix® 10 Devices
3.2. Source-Synchronous Timing Budget
3.3. Guideline: LVDS SERDES IP Core Instantiation
3.4. Guideline: LVDS SERDES Pin Pairs for Soft-CDR Mode
3.5. Guideline: LVDS Transmitters and Receivers in the Same I/O Bank
3.6. Guideline: LVDS SERDES Limitation for Stratix® 10 GX 400, SX 400, and TX 400
3.1.1. Clocking Differential Transmitters
3.1.2. Clocking Differential Receivers
3.1.3. Guideline: LVDS Reference Clock Source
3.1.4. Guideline: Use PLLs in Integer PLL Mode for LVDS
3.1.5. Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only
3.1.6. Guideline: Pin Placement for Differential Channels
3.1.7. LVDS Interface with External PLL Mode
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5.3. Comparison of LVDS SERDES Intel® FPGA IP with Stratix® V SERDES
The LVDS SERDES IP core has similar features to the Stratix® V SERDES. The key differences are the clock network and the ubiquitous RX and TX resource in LVDS I/O banks.
Features | Stratix® 10 Devices | Stratix® V Devices |
---|---|---|
Operation Frequency Range | 150 MHz - 1.6 GHz | |
Serialization/Deserialization Factors | 3 to 10 | |
Regular DPA and non-DPA mode | Supported | |
Clock Forwarding for Soft-CDR | Supported | |
RX Resource | Every I/O pair (Every two I/O pairs for CDR) |
Every two I/O pairs on every side without HSSI transceivers |
TX Resource | Every I/O pair | Every two I/O pairs every side without HSSI transceivers |
PLL Resource | TX channels can span three adjacent banks, driven by the IOPLL in the middle bank. RX channels are driven by the IOPLL in the same bank. |
RX and TX channels placed on one edge can be driven by the corner or center PLL. |
Number of DPA Clock Phase | 8 | |
I/O Standard | True LVDS | True LVDS, pseudo-differential output |