Stratix® 10 High-Speed LVDS I/O User Guide

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ID 683792
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 High-Speed LVDS I/O Overview 2. Stratix® 10 High-Speed LVDS I/O Architecture and Features 3. Stratix 10 High-Speed LVDS I/O Design Considerations 4. Stratix® 10 High-Speed LVDS I/O Implementation Guides 5. LVDS SERDES Intel® FPGA IP References 6. Stratix® 10 High-Speed LVDS I/O User Guide Archives 7. Document Revision History for the Stratix® 10 High-Speed LVDS I/O User Guide
1. Stratix® 10 High-Speed LVDS I/O Overview x
1.1. Stratix® 10 LVDS SERDES Usage Modes 1.2. Stratix® 10 LVDS Channels Support 1.3. Stratix® 10 GPIO Banks, SERDES, and DPA Locations
2. Stratix® 10 High-Speed LVDS I/O Architecture and Features x
2.1. Stratix® 10 LVDS SERDES I/O Standards Support 2.2. LVDS Transmitter Programmable I/O Features 2.3. SERDES Circuitry 2.4. Differential Transmitter in Stratix® 10 Devices 2.5. Differential Receiver in Stratix® 10 Devices
2.2. LVDS Transmitter Programmable I/O Features x
2.2.1. Programmable Pre-Emphasis 2.2.2. Programmable Differential Output Voltage
2.4. Differential Transmitter in Stratix® 10 Devices x
2.4.1. Transmitter Blocks in Stratix® 10 Devices 2.4.2. Serializer Bypass for DDR and SDR Operations
2.5. Differential Receiver in Stratix® 10 Devices x
2.5.1. Receiver Blocks in Stratix® 10 Devices 2.5.2. Receiver Modes in Stratix® 10 Devices
2.5.1. Receiver Blocks in Stratix® 10 Devices x
2.5.1.1. DPA Block 2.5.1.2. Synchronizer 2.5.1.3. Data Realignment Block (Bit Slip) 2.5.1.4. Deserializer
2.5.2. Receiver Modes in Stratix® 10 Devices x
2.5.2.1. Non-DPA Mode 2.5.2.2. DPA Mode 2.5.2.3. Soft-CDR Mode
3. Stratix 10 High-Speed LVDS I/O Design Considerations x
3.1. PLLs and Clocking for Stratix® 10 Devices 3.2. Source-Synchronous Timing Budget 3.3. Guideline: LVDS SERDES IP Core Instantiation 3.4. Guideline: LVDS SERDES Pin Pairs for Soft-CDR Mode 3.5. Guideline: LVDS Transmitters and Receivers in the Same I/O Bank 3.6. Guideline: LVDS SERDES Limitation for Stratix® 10 GX 400, SX 400, and TX 400
3.1. PLLs and Clocking for Stratix® 10 Devices x
3.1.1. Clocking Differential Transmitters 3.1.2. Clocking Differential Receivers 3.1.3. Guideline: LVDS Reference Clock Source 3.1.4. Guideline: Use PLLs in Integer PLL Mode for LVDS 3.1.5. Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only 3.1.6. Guideline: Pin Placement for Differential Channels 3.1.7. LVDS Interface with External PLL Mode
3.1.6. Guideline: Pin Placement for Differential Channels x
3.1.6.1. PLLs Driving Differential Transmitter Channels 3.1.6.2. PLLs Driving DPA-Enabled Differential Receiver Channels 3.1.6.3. PLLs Driving DPA-Enabled Differential Receiver and Transmitter Channels in LVDS Interface Spanning Multiple I/O Banks
3.1.7. LVDS Interface with External PLL Mode x
3.1.7.1. IOPLL IP Signal Interface with LVDS SERDES IP 3.1.7.2. IOPLL Parameter Values for External PLL Mode 3.1.7.3. Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode
3.2. Source-Synchronous Timing Budget x
3.2.1. Differential Data Orientation 3.2.2. Differential I/O Bit Position 3.2.3. Transmitter Channel-to-Channel Skew 3.2.4. Receiver Skew Margin for Non-DPA Mode
3.2.2. Differential I/O Bit Position x
3.2.2.1. Differential Bit Naming Conventions
3.2.4. Receiver Skew Margin for Non-DPA Mode x
3.2.4.1. RSKM Equation 3.2.4.2. Example: RSKM Calculation
3.5. Guideline: LVDS Transmitters and Receivers in the Same I/O Bank x
3.5.1. Using the Duplex Feature 3.5.2. Using an External PLL
4. Stratix® 10 High-Speed LVDS I/O Implementation Guides x
4.1. LVDS SERDES Intel® FPGA IP 4.2. LVDS SERDES IP Initialization and Reset 4.3. LVDS SERDES Intel® FPGA IP Timing 4.4. LVDS SERDES Intel® FPGA IP Design Examples 4.5. IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices
4.1. LVDS SERDES Intel® FPGA IP x
4.1.1. Release Information 4.1.2. LVDS SERDES Intel® FPGA IP Features 4.1.3. LVDS SERDES IP Core Functional Modes 4.1.4. LVDS SERDES IP Core Functional Description
4.1.4. LVDS SERDES IP Core Functional Description x
4.1.4.1. Serializer 4.1.4.2. DPA FIFO 4.1.4.3. Bitslip 4.1.4.4. Deserializer 4.1.4.5. Clock Phase Alignment
4.2. LVDS SERDES IP Initialization and Reset x
4.2.1. Initializing the LVDS SERDES IP in Non-DPA Mode 4.2.2. Initializing the LVDS SERDES IP in DPA Mode 4.2.3. Resetting the DPA 4.2.4. Word Boundaries Alignment
4.2.4. Word Boundaries Alignment x
4.2.4.1. Aligning Word Boundaries
4.3. LVDS SERDES Intel® FPGA IP Timing x
4.3.1. I/O Timing Analysis 4.3.2. FPGA Timing Analysis 4.3.3. Timing Analysis for the External PLL Mode 4.3.4. Timing Closure Guidelines for Internal FPGA Paths 4.3.5. Guideline: Use Clock Phase Alignment Block to Improve Timing Closure
4.3.1. I/O Timing Analysis x
4.3.1.1. Obtaining RSKM Report 4.3.1.2. Obtaining TCCS Report
4.4. LVDS SERDES Intel® FPGA IP Design Examples x
4.4.1. LVDS SERDES IP Synthesizable Quartus® Prime Design Examples 4.4.2. LVDS SERDES IP Simulation Design Example 4.4.3. Combined LVDS SERDES IP Transmitter and Receiver Design Example 4.4.4. LVDS SERDES IP Dynamic Phase Shift Design Example
4.5. IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices x
4.5.1. Migrating Your ALTLVDS_TX and ALTLVDS_RX IP Cores
5. LVDS SERDES Intel® FPGA IP References x
5.1. LVDS SERDES Intel® FPGA IP Parameter Settings 5.2. LVDS SERDES Intel® FPGA IP Signals 5.3. Comparison of LVDS SERDES Intel® FPGA IP with Stratix® V SERDES
5.1. LVDS SERDES Intel® FPGA IP Parameter Settings x
5.1.1. LVDS SERDES Intel® FPGA IP General Settings 5.1.2. LVDS SERDES Intel® FPGA IP PLL Settings 5.1.3. LVDS SERDES Intel® FPGA IP Receiver Settings 5.1.4. LVDS SERDES Intel® FPGA IP Transmitter Settings 5.1.5. LVDS SERDES IP Core Clock Resource Summary
5.1.3. LVDS SERDES Intel® FPGA IP Receiver Settings x
5.1.3.1. Receiver Input Clock Parameters Setup
5.1.4. LVDS SERDES Intel® FPGA IP Transmitter Settings x
5.1.4.1. Setting the Transmitter Output Clock Parameters
1. Stratix® 10 High-Speed LVDS I/O Overview
2. Stratix® 10 High-Speed LVDS I/O Architecture and Features
3. Stratix 10 High-Speed LVDS I/O Design Considerations
4. Stratix® 10 High-Speed LVDS I/O Implementation Guides
5. LVDS SERDES Intel® FPGA IP References
6. Stratix® 10 High-Speed LVDS I/O User Guide Archives
7. Document Revision History for the Stratix® 10 High-Speed LVDS I/O User Guide

7. Document Revision History for the Stratix® 10 High-Speed LVDS I/O User Guide

Document Version Quartus® Prime Version Changes
2024.07.08 24.2
  • Updated the description for Reference clock input from other I/O banks in Table: LVDS Reference Clock Source.
  • Updated Initializing the LVDS SERDES IP in DPA Mode.
  • Made minor editorial edits throughout the document.
2022.11.30 22.1 Updated the VCO Frequency information in Table: Example: Generating Output Clocks Using an IOPLL IP (Receiver in DPA or Soft-CDR Mode)
2022.03.28 22.1
  • Updated the rx_dpa_hold signal description.
  • Updated the user guide archives section. For the latest and previous versions of this user guide, refer to the Stratix® 10 High-Speed LVDS I/O User Guide.
2021.07.13 21.2 Updated the information about the receiver timing analysis in non-DPA mode.
2021.05.28 21.1 Updated the code to add to the .sdc file to specify the RCCS value.
2021.03.29 21.1 Added the IP release information.
2020.11.13 20.3
  • Updated the figure showing the I/O bank structure to add the pin naming orientation.
  • Updated the section about pin placement for differential channels to add information about sharing the dedicated reference clock input of one I/O bank to clock the PLLs in other I/O banks.
  • Updated the figure showing the PLLs driving DPA-enabled differential receiver channels to add example of an invalid PLL configuration.
2020.09.25 20.2 Removed the Use clock-pin drive parameter from the LVDS SERDES IP core general settings.
2020.07.14 20.2 Updated the figure showing the I/O bank structure:
  • Added I/O bank structure for Stratix® 10 GX 10M device
  • For I/O banks figure of other Stratix® 10 devices:
    • Marked only bank 3A as SDM shared LVDS I/O
    • Marked HPS shared LVDS I/Os
    • Added 3 V I/O banks 7A, 7B, and 7C
2020.01.03 19.4
  • Updated the programmable pre-emphasis diagram to remove the word "peak-peak".
  • Added guideline topic about LVDS SERDES limitation for Stratix® 10 GX 400, SX 400, and TX 400 devices.
2019.07.10 19.2 Corrected the clock connection to the register and rx_coreclock in the figure showing the connection for non-DPA or DPA receiver interface with the IOPLL IP core in external PLL mode.
2019.05.02 19.1
  • Moved the LVDS SERDES usage modes summary table into its own topic.
  • Updated the description of the LVDS SERDES usage modes table to improve accuracy.
  • Updated the table that lists the functional modes of the LVDS SERDES IP core to specify that all functional modes support SERDES factors of 3 to 10.
2019.02.26 18.1 Updated the guidelines for the LVDS interface with external PLL mode:
  • Combined the figures for the non-DPA and DPA modes.
  • Marked in the figures the ports that are available in CPA mode only.
  • Updated the source for the LVDS SERDES IP reset signal.
  • Updated the connection of the locked signal from the IOPLL IP to the ext_pll_locked port of the LVDS SERDES IP.
2019.01.14 18.1 Removed statement that says that the programmable VOD value of "0" is not available for the LVDS I/O standard.
2018.11.12 18.1
  • Updated the table listing the dedicated circuitries and features of the differential transmitter to clarify that the serializer width is from 3-bits to 10-bits.
  • Updated the guideline about the LVDS reference clock source to include support for reference clock input from other I/O banks.
  • Removed ext_loaden signal in figures showing the LVDS receiver in soft-CDR mode.
  • Specified that connecting the IOPLL loaden signal to the LVDS receiver ext_loaden signal is not required for LVDS receivers in soft-CDR mode.
  • Removed restriction of using the CPA block while the external PLL option is turned on.
  • Updated the topic about the timing analysis for the external PLL mode to improve clarity.
  • Updated the topic about the simulation design example to add a note about the non-synthesizable simulation driver.
  • Renamed "TimeQuest Timing Analyzer" to "Timing Analyzer".
  • Renamed "SignalTap" to "Signal Tap".
2018.08.06 18.0
  • Clarified that all LVDS SERDES IP usage modes support SERDES factors of 3 to 10.
  • Clarified that unused pins within an I/O bank with DPA feature enabled can be assigned to single ended or differential I/O standards that has the same VCCIO voltage level used by the bank in Guideline: Pin Placement for Differential Channels section.
  • Removed LVDS channels count tables in Stratix® 10 LVDS Channels Support topic and added link to Stratix® 10 pin-out files.
  • Removed the "pending characterization" labels in the topic showing the example for the RSKM calculation.
  • Updated the list of LVDS SERDES IP core features to include the CPA block.
  • Updated outclk2 to outclk4 in all examples of using the LVDS interfaces in external PLL mode.
  • Updated tables and examples for IOPLL and LVDS SERDES IP cores signals in external PLL mode to include information about using the IP cores with the CPA block turned on.
  • Updated the LVDS SERDES IP core instantiation guideline to specify that you can use multiple LVDS SERDES IP cores instance per I/O bank in any functional mode by using an external PLL.
  • Corrected typographical error—changed tx_inclock to rx_inclock—in the topic about the deserializer.
  • Updated the figures descriptions in the guideline topic about using external PLL to use LVDS transmitters and receivers in the same I/O bank to clarify that the figures show connections that you need to make.
  • Added topic about the CPA block under the Functional Description section. Moved information from the CPA feature guideline topic to this new topic.
  • Updated the guideline topic about using the CPA feature to move information to a new CPA topic. Added link to the new topic.
  • Updated the synthesizable design example topic to improve clarity and add duplex mode.
  • Corrected the combined receiver and transmitter design example topic to specify that it creates an external PLL. The combined transmitter and receiver design example does not support the duplex feature.
  • Updated the dynamic phase shift design example topic to specify that the design example does not support the duplex feature.
  • Updated the LVDS SERDES IP core general settings reference topic to clarify the number of channels in the Duplex Feature mode and to update the CPA feature parameter name.
  • Updated the names of the following IP cores:
    • Intel FPGA LVDS SERDES to LVDS SERDES Intel FPGA IP
    • Intel FPGA IOPLL to IOPLL Intel FPGA IP
    • Intel FPGA GPIO to GPIO Intel FPGA IP
Date Version Changes
November 2017 2017.11.06
  • Added the duplex feature option that allows you to place transmitters and receivers in the same I/O bank using a single instance of the LVDS SERDES IP core.
  • Removed the HF50 package from all Stratix® 10 devices.
  • Added package SF48 to Stratix® 10 TX 1650 and TX 2100 devices.
  • Removed Stratix® 10 TX 4500 and TX 5500 devices.
  • Added Stratix® 10 MX devices.
  • Updated descriptions of the tables that list the LVDS channels support to specify that the LVDS channels counts include dedicated clock pins.
  • Changed all instances of the following IP names:
    • Altera LVDS SERDES to Intel FPGA LVDS SERDES
    • Altera IOPLL to Intel FPGA IOPLL
    • Altera GPIO to Intel FPGA GPIO
  • Renamed "Qsys" to Platform Designer.
  • Removed the statement about selecting the rising edge option in the parameter editor for the RX Non-DPA mode.
  • Updated the topic about clocking differential transmitters to improve clarity about transmitter placement limitation in relations to the tx_outclock phase shift.
  • Restructured the information in the topic about connecting the external PLL to the LVDS receiver and transmitter. Moved some of the information to the guideline topic about using external PLL for combined LVDS transmitters and receivers in the same I/O bank.
  • Rewrote the guideline topic about using external PLL for combined LVDS transmitters and receivers in the same I/O bank. The topic now describes using either an external PLL or the duplex feature of the LVDS SERDES IP core.
  • Added quick guidelines about using the SERDES in the topic that provides an overview of the high-speed LVDS I/O.
  • Updated the note about driving LVDS channels with the PLL in integer PLL mode to clarify that you do not need a PLL if you bypass the SERDES.
  • Updated the topic about the serializer bypass for DDR and SDR operation to add more information about clocks to the IOE.
  • Updated the topic about the deserializer to add more information about bypassing the deserializer.
  • Removed the statement about SDR and DDR data width from the figures that show the receiver datapath in non-DPA, DPA, and soft-CDR modes.
  • Corrected typographical error in the example showing the parameter values to generate output clock in external PLL mode by updating "c0" to "outclk0".
  • Added more description for the Enable tx_coreclock port parameter option to describe how configure it in external PLL mode, and the effect of turning on the clock phase alignment block.
  • Updated the description of the tx_coreclock signal.
  • Removed the RSKM Report for LVDS Receiver and Assigning Input Delay to LVDS Receiver Using TimeQuest Timing Analyzer topics and added a related link to Obtaining RSKM Report topic instead.
  • Updated the topic about the combined transmitter and receiver design example to specify that the design example uses the duplex mode feature.
  • Added guideline topic about LVDS reference clock source.
  • Added a note about using external PLL with a wide transmitter interface that spans multiple I/O banks.
  • Updated the Use the CPA block for improved periphery-core timing for even SERDES Factors IP core parameter option to update the label and specify that it is now available for any selectable SERDES factor.
May 2017 2017.05.08
  • Updated the timing diagram that shows the DPA clock phase to serial data timing relationship to align the clock phases with the data.
  • Updated the topic about the LVDS interface with external PLL mode to clarify that the Clock Resource Summary tab in the LVDS SERDES IP core parameter editor provides the details for the signals required from the GPIO IP core.
  • Added guideline topic about using external PLL for LVDS transmitter and receiver interfaces combined in an I/O bank.
  • Added guideline topic about using the clock phase alignment block to improve periphery-core timing.
  • Updated the description for the Number of channels parameter in the table listing the LVDS SERDES General Settings tab to improve clarity and specify the placement of the refclk and tx_outclock pins.
  • Added the "Use the clock phase alignment block for improved periphery-core timing for even SERDES factors" IP core parameter option.
February 2017 2017.02.13 Removed the SF48 package from the Stratix® 10 TX 1650 and TX 2100 devices.
October 2016 2016.10.31 Initial release.
Level Two Title