Stratix® 10 GX/SX Device Overview

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ID 683729
Date 6/28/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 GX/SX Device Overview
1. Stratix® 10 GX/SX Device Overview x
1.1. Stratix® 10 GX/SX Family Variants 1.2. Innovations in Stratix® 10 FPGAs and SoCs 1.3. FPGA and SoC Features Summary 1.4. Stratix® 10 Block Diagram 1.5. Stratix® 10 FPGA and SoC Family Plan 1.6. Hyperflex® Core Architecture 1.7. Heterogeneous 3D SiP Transceiver Tiles 1.8. Stratix® 10 Transceivers 1.9. PCI Express Gen1/Gen2/Gen3 Hard IP 1.10. Interlaken PCS Hard IP 1.11. 10G Ethernet Hard IP 1.12. External Memory and General Purpose I/O 1.13. Adaptive Logic Module (ALM) 1.14. Core Clocking 1.15. Fractional Synthesis PLLs and I/O PLLs 1.16. Internal Embedded Memory 1.17. Variable Precision DSP Block 1.18. Hard Processor System (HPS) 1.19. Power Management 1.20. Device Configuration and Secure Device Manager (SDM) 1.21. Device Security 1.22. Configuration via Protocol Using PCI Express* 1.23. Partial and Dynamic Reconfiguration 1.24. Fast Forward Compile 1.25. Single Event Upset (SEU) Error Detection and Correction 1.26. Document Revision History for the Stratix® 10 GX/SX Device Overview
1.1. Stratix® 10 GX/SX Family Variants x
1.1.1. Available Options
1.8. Stratix® 10 Transceivers x
1.8.1. PMA Features 1.8.2. PCS Features
1.18. Hard Processor System (HPS) x
1.18.1. Key Features of the Stratix® 10 HPS
1. Stratix® 10 GX/SX Device Overview

1.5. Stratix® 10 FPGA and SoC Family Plan

Table 4.   Stratix® 10 GX/SX FPGA and SoC Family Plan—FPGA Core (part 1)

Stratix® 10 GX/SX Device Name

Logic Elements (KLE)

M20K Blocks

M20K Mbits

MLAB Counts

MLAB Mbits

18x19 Multi- pliers 2

GX 400/

SX 400

378 1,537 30 3,276 2 1,296

GX 650/

SX 650

612 2,489 49 5,364 3 2,304

GX 850/

SX 850

841 3,477 68 7,124 4 4,032

GX 1100/

SX 1100

1,325 5,461 107 11,556 7 5,184

GX 1650/

SX 1650

1,624 5,851 114 13,764 8 6,290

GX 2100/

SX 2100

2,005 6,501 127 17,316 11 7,488

GX 2500/

SX 2500

2,422 9,963 195 20,529 13 10,022

GX 2800/

SX 2800

2,753 11,721 229 23,796 15 11,520

GX 1660

 1,679 6,162 120 14,230 9 6,652

GX 2110

 2,073 6,847 134 17,856 11 7,920
GX 10M 10,200 12,950 253 87,984 55 6,912
Table 5.   Stratix® 10 GX/SX FPGA and SoC Family Plan—Interconnects, PLLs and Hard IP (part 2)

Stratix® 10 GX/SX Device Name

Interconnects PLLs Hard IP
Maximum GPIOs Maximum XCVR fPLLs I/O PLLs PCIe Hard IP Blocks

GX 400/

SX 400

 374 24 8 8 1

GX 650/

SX 650

 392 24 8 8 1

GX 850/

SX 850

 688 48 16 16 2

GX 1100/

SX 1100

 688 48 16 16 2

GX 1650/

SX 1650

 704 96 32 24 4

GX 2100/

SX 2100

 704 96 32 24 4

GX 2500/

SX 2500

 1,160 96 32 24 4

GX 2800/

SX 2800

 1,160 96 32 24 4

GX 1660

688 48 16 16 2

GX 2110

688 48 16 16 2
GX 10M 2,304 48 24 48 4

Table 6.   Stratix® 10 GX/SX FPGA and SoC Family Package Plan Cell legend: General Purpose I/Os, High-Voltage I/Os, LVDS Pairs, Transceivers 3 4 5 6 7 8

Stratix® 10 GX/SX Device Name

F1152

HF35

(35x35 mm2)

F1760

NF43

(42.5x42.5 mm2)

F2397

UF50

(50x50 mm2)

F2912

HF55

(55x55 mm2)

F4938

NF74

(70x74 mm2

GX 400/

SX 400

374, 56, 120, 249 — — — —

GX 650/

SX 650

392, 8, 192, 24 — — — —

GX 850/

SX 850

— 688, 16, 336, 48 — — —

GX 1100/

SX 1100

— 688, 16, 336, 48 — — —

GX 1650/

SX 1650

— 688, 16, 336, 48 704, 32, 336, 96 — —

GX 2100/

SX 2100

— 688, 16, 336, 48 704, 32, 336, 96 — —

GX 2500/

SX 2500

— 688, 16, 336, 48 704, 32, 336, 96 1160, 8, 576, 24 ——

GX 2800/

SX 2800

— 688, 16, 336, 48 704, 32, 336, 96 1160, 8, 576, 24 —

GX 1660

 — 688, 16, 336, 48 — — —

GX 2110

 — 688, 16, 336, 48 — — —
GX 10M — — — — 2304, 32, 1152, 48
Figure 3.  Stratix® 10 SX/GX 400 Device Level Shifter Details
Related Information
2 The number of 27x27 multipliers is one-half the number of 18x19 multipliers.
3 All packages are ball grid arrays with 1.0 mm pitch.
4 High-Voltage I/O pins are used for 3 V and 2.5 V interfacing.
5 Each LVDS pair can be configured as either a differential input or a differential output.
6 High-Voltage I/O pins and LVDS pairs are included in the General Purpose I/O count. Transceivers are counted separately.
7 Each package column offers pin migration (common circuit board footprint) for all devices in the column. For more information about vertical migration and the common circuit board footprint, see Vertical Device Migration in Stratix® 10 Device Design Guidelines.
8 Stratix® 10 GX devices are pin migratable with Stratix® 10 SX devices in the same package.
9 The Stratix® 10 SX/GX 400 device has a level shifter, and this imposes some restrictions on the number of LVDS pairs and I/O banks available (see " Stratix® 10 SX/GX 400 Device Level Shifter Details").
Level Two Title