Stratix® 10 GX/SX Device Overview

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ID 683729
Date 6/28/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 GX/SX Device Overview
1. Stratix® 10 GX/SX Device Overview x
1.1. Stratix® 10 GX/SX Family Variants 1.2. Innovations in Stratix® 10 FPGAs and SoCs 1.3. FPGA and SoC Features Summary 1.4. Stratix® 10 Block Diagram 1.5. Stratix® 10 FPGA and SoC Family Plan 1.6. Hyperflex® Core Architecture 1.7. Heterogeneous 3D SiP Transceiver Tiles 1.8. Stratix® 10 Transceivers 1.9. PCI Express Gen1/Gen2/Gen3 Hard IP 1.10. Interlaken PCS Hard IP 1.11. 10G Ethernet Hard IP 1.12. External Memory and General Purpose I/O 1.13. Adaptive Logic Module (ALM) 1.14. Core Clocking 1.15. Fractional Synthesis PLLs and I/O PLLs 1.16. Internal Embedded Memory 1.17. Variable Precision DSP Block 1.18. Hard Processor System (HPS) 1.19. Power Management 1.20. Device Configuration and Secure Device Manager (SDM) 1.21. Device Security 1.22. Configuration via Protocol Using PCI Express* 1.23. Partial and Dynamic Reconfiguration 1.24. Fast Forward Compile 1.25. Single Event Upset (SEU) Error Detection and Correction 1.26. Document Revision History for the Stratix® 10 GX/SX Device Overview
1.1. Stratix® 10 GX/SX Family Variants x
1.1.1. Available Options
1.8. Stratix® 10 Transceivers x
1.8.1. PMA Features 1.8.2. PCS Features
1.18. Hard Processor System (HPS) x
1.18.1. Key Features of the Stratix® 10 HPS
1. Stratix® 10 GX/SX Device Overview

1.9. PCI Express Gen1/Gen2/Gen3 Hard IP

Stratix® 10 devices contain embedded PCI Express hard IP designed for performance, ease-of-use, increased functionality, and designer productivity.

The PCI Express hard IP consists of the PHY, Data Link, and Transaction layers. It also supports PCI Express Gen1/Gen2/Gen3 end point and root port, in x1/x2/x4/x8/x16 lane configurations. The PCI Express hard IP is capable of operating independently from the core logic (autonomous mode). This feature allows the PCI Express link to power up and complete link training in less than 100 ms, while the rest of the device is still in the process of being configured. The hard IP also provides added functionality, which makes it easier to support emerging features such as Single Root I/O Virtualization (SR-IOV) and optional protocol extensions.

The PCI Express hard IP has improved end-to-end data path protection using Error Checking and Correction (ECC). In addition, the hard IP supports configuration of the device via protocol (CvP) across the PCI Express bus at Gen1/Gen2/Gen3 rates.

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