Stratix® 10 GX/SX Device Overview

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ID 683729
Date 6/28/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 GX/SX Device Overview
1. Stratix® 10 GX/SX Device Overview x
1.1. Stratix® 10 GX/SX Family Variants 1.2. Innovations in Stratix® 10 FPGAs and SoCs 1.3. FPGA and SoC Features Summary 1.4. Stratix® 10 Block Diagram 1.5. Stratix® 10 FPGA and SoC Family Plan 1.6. Hyperflex® Core Architecture 1.7. Heterogeneous 3D SiP Transceiver Tiles 1.8. Stratix® 10 Transceivers 1.9. PCI Express Gen1/Gen2/Gen3 Hard IP 1.10. Interlaken PCS Hard IP 1.11. 10G Ethernet Hard IP 1.12. External Memory and General Purpose I/O 1.13. Adaptive Logic Module (ALM) 1.14. Core Clocking 1.15. Fractional Synthesis PLLs and I/O PLLs 1.16. Internal Embedded Memory 1.17. Variable Precision DSP Block 1.18. Hard Processor System (HPS) 1.19. Power Management 1.20. Device Configuration and Secure Device Manager (SDM) 1.21. Device Security 1.22. Configuration via Protocol Using PCI Express* 1.23. Partial and Dynamic Reconfiguration 1.24. Fast Forward Compile 1.25. Single Event Upset (SEU) Error Detection and Correction 1.26. Document Revision History for the Stratix® 10 GX/SX Device Overview
1.1. Stratix® 10 GX/SX Family Variants x
1.1.1. Available Options
1.8. Stratix® 10 Transceivers x
1.8.1. PMA Features 1.8.2. PCS Features
1.18. Hard Processor System (HPS) x
1.18.1. Key Features of the Stratix® 10 HPS
1. Stratix® 10 GX/SX Device Overview

1.25. Single Event Upset (SEU) Error Detection and Correction

Stratix® 10 FPGAs and SoCs offer robust SEU error detection and correction circuitry. The detection and correction circuitry includes protection for Configuration RAM (CRAM) programming bits and user memories. The CRAM is protected by a continuously running parity checker circuit with integrated ECC that automatically corrects one or two bit errors and detects higher order multibit errors.

The physical layout of the CRAM array is optimized to make the majority of multi-bit upsets appear as independent single-bit or double-bit errors which are automatically corrected by the integrated CRAM ECC circuitry. In addition to the CRAM protection, user memories also include integrated ECC circuitry and are layout optimized for error detection and correction.

The SEU error detection and correction hardware is supported by both soft IP and the Quartus® Prime software to provide a complete SEU mitigation solution. The components of the complete solution include:

  • Hard error detection and correction for CRAM and user M20K memory blocks
  • Optimized physical layout of memory cells to minimize probability of SEU
  • Sensitivity processing soft IP that reports if CRAM upset affects a used or unused bit
  • Fault injection soft IP with the Quartus® Prime software support that changes state of CRAM bits for testing purposes
  • Hierarchy tagging in the Quartus® Prime software
  • Triple Mode Redundancy (TMR) used for the Secure Device Manager and critical on-chip state machines

In addition to the SEU mitigation features listed above, the Intel 14 nm tri-gate process technology used for Stratix® 10 devices is based on FinFET transistors which have reduced SEU susceptibility versus conventional planar transistors.

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