Stratix® 10 GX/SX Device Overview

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ID 683729
Date 6/28/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 GX/SX Device Overview
1. Stratix® 10 GX/SX Device Overview x
1.1. Stratix® 10 GX/SX Family Variants 1.2. Innovations in Stratix® 10 FPGAs and SoCs 1.3. FPGA and SoC Features Summary 1.4. Stratix® 10 Block Diagram 1.5. Stratix® 10 FPGA and SoC Family Plan 1.6. Hyperflex® Core Architecture 1.7. Heterogeneous 3D SiP Transceiver Tiles 1.8. Stratix® 10 Transceivers 1.9. PCI Express Gen1/Gen2/Gen3 Hard IP 1.10. Interlaken PCS Hard IP 1.11. 10G Ethernet Hard IP 1.12. External Memory and General Purpose I/O 1.13. Adaptive Logic Module (ALM) 1.14. Core Clocking 1.15. Fractional Synthesis PLLs and I/O PLLs 1.16. Internal Embedded Memory 1.17. Variable Precision DSP Block 1.18. Hard Processor System (HPS) 1.19. Power Management 1.20. Device Configuration and Secure Device Manager (SDM) 1.21. Device Security 1.22. Configuration via Protocol Using PCI Express* 1.23. Partial and Dynamic Reconfiguration 1.24. Fast Forward Compile 1.25. Single Event Upset (SEU) Error Detection and Correction 1.26. Document Revision History for the Stratix® 10 GX/SX Device Overview
1.1. Stratix® 10 GX/SX Family Variants x
1.1.1. Available Options
1.8. Stratix® 10 Transceivers x
1.8.1. PMA Features 1.8.2. PCS Features
1.18. Hard Processor System (HPS) x
1.18.1. Key Features of the Stratix® 10 HPS
1. Stratix® 10 GX/SX Device Overview

1.21. Device Security

Building on top of the robust security features present in the previous generation devices, Stratix® 10 FPGAs and SoCs include a number of new and innovative security enhancements. These features are also managed by the SDM, tightly coupling device configuration and reconfiguration with encryption, authentication, key storage and anti-tamper services.

Security services provided by the SDM include:

  • Bitstream encryption
  • Multi-factor authentication
  • Hard encryption and authentication acceleration; AES-256, SHA-256/384, ECDSA-256/384
  • Volatile and non-volatile encryption key storage and management
  • Boot code authentication for the HPS
  • Physically Unclonable Function (PUF) service
  • Updateable configuration process
  • Secure device maintenance and upgrade functions
  • Side channel attack protection
  • Scripted response to sensor inputs and security attacks, including selective sector zeroization
  • Readback, JTAG and test mode disable
  • Enhanced response to single-event upsets (SEU)
  • Black key provisioning
  • Physical anti-tamper

Refer to the Security Overview for SDM-Based FPGA Devices for a complete list of all security features.

The SDM and associated security services provide a robust, multi-layered security solution for your Stratix® 10 design.

Table 14.  Device Security
Stratix® 10 Family Variant Bitstream Authentication Advanced Security Features 12
GX/SX All devices -AS suffix part number required
Related Information
12 Contact My Intel Support for additional information.
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