Stratix® 10 GX/SX Device Overview

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ID 683729
Date 6/28/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 GX/SX Device Overview
1. Stratix® 10 GX/SX Device Overview x
1.1. Stratix® 10 GX/SX Family Variants 1.2. Innovations in Stratix® 10 FPGAs and SoCs 1.3. FPGA and SoC Features Summary 1.4. Stratix® 10 Block Diagram 1.5. Stratix® 10 FPGA and SoC Family Plan 1.6. Hyperflex® Core Architecture 1.7. Heterogeneous 3D SiP Transceiver Tiles 1.8. Stratix® 10 Transceivers 1.9. PCI Express Gen1/Gen2/Gen3 Hard IP 1.10. Interlaken PCS Hard IP 1.11. 10G Ethernet Hard IP 1.12. External Memory and General Purpose I/O 1.13. Adaptive Logic Module (ALM) 1.14. Core Clocking 1.15. Fractional Synthesis PLLs and I/O PLLs 1.16. Internal Embedded Memory 1.17. Variable Precision DSP Block 1.18. Hard Processor System (HPS) 1.19. Power Management 1.20. Device Configuration and Secure Device Manager (SDM) 1.21. Device Security 1.22. Configuration via Protocol Using PCI Express* 1.23. Partial and Dynamic Reconfiguration 1.24. Fast Forward Compile 1.25. Single Event Upset (SEU) Error Detection and Correction 1.26. Document Revision History for the Stratix® 10 GX/SX Device Overview
1.1. Stratix® 10 GX/SX Family Variants x
1.1.1. Available Options
1.8. Stratix® 10 Transceivers x
1.8.1. PMA Features 1.8.2. PCS Features
1.18. Hard Processor System (HPS) x
1.18.1. Key Features of the Stratix® 10 HPS
1. Stratix® 10 GX/SX Device Overview

1.17. Variable Precision DSP Block

The Stratix® 10 DSP blocks are based upon the Variable Precision DSP Architecture used in Altera’s previous generation devices. They feature hard fixed point and IEEE 754 compliant floating point capability.

The DSP blocks can be configured to support signal processing with precision ranging from 18x19 up to 54x54. A pipeline register has been added to increase the maximum operating frequency of the DSP block and reduce power consumption.

Figure 12. DSP Block: Standard Precision Fixed Point Mode
Figure 13. DSP Block: High Precision Fixed Point Mode
Figure 14. DSP Block: Single Precision Floating Point Mode

Each DSP block can be independently configured at compile time as either dual 18x19 or a single 27x27 multiply accumulate. With a dedicated 64 bit cascade bus, multiple variable precision DSP blocks can be cascaded to implement even higher precision DSP functions efficiently.

In floating point mode, each DSP block provides one single precision floating point multiplier and adder. Floating point additions, multiplications, mult-adds and mult-accumulates are supported.

The following table shows how different precisions are accommodated within a DSP block, or by utilizing multiple blocks.

Table 11.   Variable Precision DSP Block Configurations

Multiplier Size

DSP Block Resources

Expected Usage

18x19 bits

1/2 of Variable Precision DSP Block

Medium precision fixed point

27x27 bits

1 Variable Precision DSP Block

High precision fixed point

19x36 bits

1 Variable Precision DSP Block with external adder

Fixed point FFTs

36x36 bits

2 Variable Precision DSP Blocks with external adder

Very high precision fixed point

54x54 bits

4 Variable Precision DSP Blocks with external adder

Double Precision floating point

Single Precision floating point 1 Single Precision floating point adder, 1 Single Precision floating point multiplier Floating point

Complex multiplication is very common in DSP algorithms. One of the most popular applications of complex multipliers is the FFT algorithm. This algorithm has the characteristic of increasing precision requirements on only one side of the multiplier. The Variable Precision DSP block supports the FFT algorithm with proportional increase in DSP resources as the precision grows.

Table 12.  Complex Multiplication With Variable Precision DSP Block

Complex Multiplier Size

DSP Block Resources

FFT Usage

18x19 bits

2 Variable Precision DSP Blocks

Resource optimized FFT

27x27 bits

4 Variable Precision DSP Blocks

Highest precision FFT

For FFT applications with high dynamic range requirements, the Altera FFT IP Core offers an option of single precision floating point implementation with resource usage and performance similar to high precision fixed point implementations.

Other features of the DSP block include:

  • Hard 18 bit and 25 bit pre-adders
  • Hard floating point multipliers and adders
  • 64 bit dual accumulator (for separate I, Q product accumulations)
  • Cascaded output adder chains for 18 and 27 bit FIR filters
  • Embedded coefficient registers for 18 and 27 bit coefficients
  • Fully independent multiplier outputs
  • Inferability using HDL templates supplied by the Quartus® Prime software for most modes

The Variable Precision DSP block is ideal to support the growing trend towards higher bit precision in high performance DSP applications. At the same time, it can efficiently support the many existing 18 bit DSP applications, such as high definition video processing and remote radio heads. With the Variable Precision DSP block architecture and hard floating point multipliers and adders, Stratix® 10 devices can efficiently support many different precision levels up to and including floating point implementations. This flexibility can result in increased system performance, reduced power consumption, and reduce architecture constraints on system algorithm designers.

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