1.2. Innovations in Stratix® 10 FPGAs and SoCs
Stratix® 10 FPGAs and SoCs deliver many significant improvements over the previous generation high-performance Stratix® V FPGAs.
| Feature | Stratix® V FPGAs | Stratix® 10 FPGAs and SoCs |
|---|---|---|
| Process technology | 28 nm TSMC (planar transistor) | 14 nm Intel tri-gate (FinFET) |
| Hard processor core | None | Quad-core 64 bit Arm* Cortex* -A53 (SoC only) |
| Core architecture | Conventional core architecture with conventional interconnect | Hyperflex® core architecture with Hyper-Registers in the interconnect |
| Core performance | 500 MHz | 1 GHz |
| Power dissipation | 1x | As low as 0.3x |
| Logic density | 952 KLE | 10,200 KLE |
| Embedded memory (M20K) | 52 Mbits | 253 Mbits |
| 18x19 multipliers | 3,926
Note: Multiplier is 18x18 in Stratix® V devices.
|
11,520
Note: Multiplier is 18x19 in Stratix® 10 devices.
|
| Floating point DSP capability | Up to 1 TFLOP, requires soft floating point adder and multiplier | Up to 10 TFLOP, hard IEEE 754 compliant single precision floating point adder and multiplier |
| Maximum transceivers | 66 | 96 |
| Maximum transceiver data rate (chip-to-chip) | 28.05 Gbps | 26.6 Gbps L-Tile 28.3 Gbps H-Tile |
| Maximum transceiver data rate (backplane) | 12.5 Gbps | 12.5 Gbps L-Tile 28.3 Gbps H-Tile |
| Hard memory controller | None | DDR4 @ 1333 MHz/2666 Mbps DDR3 @ 1067 MHz/2133 Mbps |
| Hard protocol IP | PCIe* Gen3 x8 (up to 4 instances) | PCIe* Gen3 x16 (up to 4 instances) SR-IOV (4 physical functions / 2k virtual functions) on H-Tile devices 10GBASE-KR/40GBASE-KR4 FEC |
| Core clocking and PLLs | Global, quadrant and regional clocks supported by fractional-synthesis fPLLs | Programmable clock tree synthesis supported by fractional synthesis fPLLs and integer IO PLLs |
These innovations result in the following improvements:
- Improved Core Logic Performance: The Hyperflex® core architecture combined with 14 nm Intel tri-gate technology allows Stratix® 10 devices to achieve 2X the core performance compared to the previous generation
- Lower Power: Stratix® 10 devices use up to 70% lower power compared to the previous generation, enabled by 14 nm Intel tri-gate technology, the Hyperflex® core architecture, and optional power saving features built into the architecture
- Higher Density: Stratix® 10 devices offer three times the level of integration, with up to 10.2 million logic elements (LEs), over 253 Mbits of embedded memory blocks (M20K), and 11,520 18x19 multipliers
- Embedded Processing: Stratix® 10 SoCs feature a Quad-Core 64 bit Arm* Cortex* -A53 processor optimized for power efficiency and software compatible with previous generation Arria® and Cyclone® SoC devices
- Improved Transceiver Performance: With up to 96 transceiver channels implemented in heterogeneous 3D SiP transceiver tiles, Stratix® 10 GX and SX devices support data rates up to 28.3 Gbps chip-to-chip and 28.3 Gbps across the backplane with signal conditioning circuits capable of equalizing over 30 dB of system loss
- Improved DSP Performance: The variable precision DSP block in Stratix® 10 devices features hard fixed and floating point capability, with up to 10 TFLOP IEEE754 single-precision floating point performance
- Additional Hard IP: Stratix® 10 devices include many more hard IP blocks than previous generation devices, with a hard memory controller included in each bank of 48 general purpose IOs, a hard PCIe* Gen3 x16 full protocol stack in each transceiver tile, and a hard 10GBASE-KR/40GBASE-KR4 FEC in every transceiver channel
- Enhanced Core Clocking: Stratix® 10 devices feature programmable clock tree synthesis; clock trees are only synthesized where needed, increasing the flexibility and reducing the power dissipation of the clocking solution
- Additional Core PLLs: The core fabric in Stratix® 10 devices is supported by both integer IO PLLs and fractional synthesis fPLLs, resulting in a greater total number of PLLs available than the previous generation