Stratix® 10 GX/SX Device Overview

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ID 683729
Date 6/28/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 GX/SX Device Overview
1. Stratix® 10 GX/SX Device Overview x
1.1. Stratix® 10 GX/SX Family Variants 1.2. Innovations in Stratix® 10 FPGAs and SoCs 1.3. FPGA and SoC Features Summary 1.4. Stratix® 10 Block Diagram 1.5. Stratix® 10 FPGA and SoC Family Plan 1.6. Hyperflex® Core Architecture 1.7. Heterogeneous 3D SiP Transceiver Tiles 1.8. Stratix® 10 Transceivers 1.9. PCI Express Gen1/Gen2/Gen3 Hard IP 1.10. Interlaken PCS Hard IP 1.11. 10G Ethernet Hard IP 1.12. External Memory and General Purpose I/O 1.13. Adaptive Logic Module (ALM) 1.14. Core Clocking 1.15. Fractional Synthesis PLLs and I/O PLLs 1.16. Internal Embedded Memory 1.17. Variable Precision DSP Block 1.18. Hard Processor System (HPS) 1.19. Power Management 1.20. Device Configuration and Secure Device Manager (SDM) 1.21. Device Security 1.22. Configuration via Protocol Using PCI Express* 1.23. Partial and Dynamic Reconfiguration 1.24. Fast Forward Compile 1.25. Single Event Upset (SEU) Error Detection and Correction 1.26. Document Revision History for the Stratix® 10 GX/SX Device Overview
1.1. Stratix® 10 GX/SX Family Variants x
1.1.1. Available Options
1.8. Stratix® 10 Transceivers x
1.8.1. PMA Features 1.8.2. PCS Features
1.18. Hard Processor System (HPS) x
1.18.1. Key Features of the Stratix® 10 HPS
1. Stratix® 10 GX/SX Device Overview

1.3. FPGA and SoC Features Summary

Table 2.   Stratix® 10 FPGA and SoC Common Device Features

Feature

Description

Technology

  • 14 nm Intel tri-gate (FinFET) process technology
  • SmartVID controlled core voltage, standard power devices
  • 0.85-V fixed core voltage, low static power devices available

Low power serial transceivers

  • Up to 96 total transceivers available
  • Continuous operating range of 1 Gbps to 28.3 Gbps for Stratix® 10 GX/SX devices
  • Backplane support up to 28.3 Gbps for Stratix® 10 GX/SX devices
  • Extended range down to 125 Mbps with oversampling
  • ATX transmit PLLs with user-configurable fractional synthesis capability
  • XFP, SFP+, QSFP/QSFP28, CFP/CFP2/CFP4 optical module support
  • Adaptive linear and decision feedback equalization
  • Transmit pre-emphasis and de-emphasis
  • Dynamic partial reconfiguration of individual transceiver channels
  • On-chip instrumentation (Eye Viewer non-intrusive data eye monitoring)

General purpose I/Os

  • Up to 2,304 total GPIO available
  • 1.6 Gbps LVDS—every pair can be configured as an input or output
  • 1333 MHz/2666 Mbps DDR4 external memory interface
  • 1067 MHz/2133 Mbps DDR3 external memory interface
  • 1.2 V to 3.3 V1 single-ended LVCMOS/LVTTL interfacing
  • On-chip termination (OCT)

Embedded hard IP

  • PCIe Gen1/Gen2/Gen3 complete protocol stack, x1/x2/x4/x8/x16 end point and root port
  • DDR4/DDR3 hard memory controller (RLDRAM3/QDR II+/QDR IV using soft memory controller)
  • Multiple hard IP instantiations in each device
  • Single Root I/O Virtualization (SR-IOV)

Transceiver hard IP

  • 10GBASE-KR/40GBASE-KR4 Forward Error Correction (FEC)
  • 10G Ethernet PCS
  • PCI Express* PIPE interface
  • Interlaken PCS
  • Gigabit Ethernet PCS
  • Deterministic latency support for Common Public Radio Interface (CPRI) PCS
  • Fast lock-time support for Gigabit Passive Optical Networking (GPON) PCS
  • 8B/10B, 64B/66B, 64B/67B encoders and decoders
  • Custom mode support for proprietary protocols

Power management

  • SmartVID controlled core voltage, standard power devices
  • 0.85-V fixed core voltage, low static power devices available
  • Quartus® Prime Pro Edition integrated power analysis

High performance core fabric

  • Hyperflex® core architecture with Hyper-Registers throughout the interconnect routing and at the inputs of all functional blocks
  • Enhanced adaptive logic module (ALM)
  • Improved multi-track routing architecture reduces congestion and improves compile times
  • Hierarchical core clocking architecture with programmable clock tree synthesis
  • Fine-grained partial reconfiguration

Internal memory blocks

  • M20K—20 Kb with hard ECC support
  • MLAB—640 bit distributed LUTRAM

Variable precision DSP blocks

  • IEEE 754-compliant hard single-precision floating point capability
  • Supports signal processing with precision ranging from 18x19 up to 54x54
  • Native 27x27 and 18x19 multiply modes
  • 64 bit accumulator and cascade for systolic FIRs
  • Internal coefficient memory banks
  • Pre-adder/subtractor improves efficiency
  • Additional pipeline register increases performance and reduces power

Phase locked loops (PLL)

  • Fractional synthesis PLLs (fPLL) support both fractional and integer modes
  • Fractional mode with third-order delta-sigma modulation
  • Precision frequency synthesis
  • Integer PLLs adjacent to general purpose I/Os, support external memory, and LVDS interfaces, clock delay compensation, zero delay buffering

Core clock networks

  • 1 GHz fabric clocking
  • 667 MHz external memory interface clocking, supports 2666 Mbps DDR4 interface
  • 800 MHz LVDS interface clocking, supports 1600 Mbps LVDS interface
  • Programmable clock tree synthesis, backwards compatible with global, regional and peripheral clock networks
  • Clocks only synthesized where needed, to minimize dynamic power

Configuration

  • Dedicated Secure Device Manager
  • Software programmable device configuration
  • Serial and parallel flash interface
  • Configuration via protocol (CvP) using PCI Express Gen1/Gen2/Gen3
  • Fine-grained partial reconfiguration of core fabric
  • Dynamic reconfiguration of transceivers and PLLs
  • Comprehensive set of security features including AES-256, SHA-256/384, and ECDSA-256/384 accelerators, and multi-factor authentication
  • Physically Unclonable Function (PUF) service

Packaging

  • Intel Embedded Multi-die Interconnect Bridge (EMIB) packaging technology
  • Multiple devices with identical package footprints allows seamless migration across different device densities
  • 1.0 mm ball-pitch FBGA packaging
  • Lead and lead-free package options

Software and tools

  • Quartus® Prime Pro Edition design suite with new compiler and Hyper-Aware design flow
  • Fast Forward compiler to allow Hyperflex® architecture performance exploration
  • Transceiver toolkit
  • Platform designer integration tool
  • DSP Builder advanced blockset
  • OpenCL™ support
  • SoC Embedded Design Suite (EDS)
Table 3.   Stratix® 10 SoC Specific Device Features
SoC Subsystem Feature Description
Hard Processor System Multi-processor unit (MPU) core
  • Quad-core Arm* Cortex* -A53 MPCore processor with Arm* CoreSight* debug and trace technology
  • Scalar floating-point unit supporting single and double precision
  • Arm* Neon* media processing engine for each processor
System Controllers
  • System Memory Management Unit (SMMU)
  • Cache Coherency Unit (CCU)
Layer 1 Cache
  • 32 KB L1 instruction cache with parity
  • 32 KB L1 data cache with ECC
Layer 2 Cache
  • 1 MB Shared L2 Cache with ECC
On-Chip Memory
  • 256 KB On-Chip RAM
Direct memory access (DMA) controller
  • 8-Channel DMA
Ethernet media access controller (EMAC)
  • Three 10/100/1000 EMAC with integrated DMA
USB On-The-Go controller (OTG)
  • 2 USB OTG with integrated DMA
UART controller
  • 2 UART 16550 compatible
Serial Peripheral Interface (SPI) controller
  • 4 SPI
I2C controller
  • 5 I2C controllers
SD/SDIO/MMC controller
  • 1 eMMC version 4.5 with DMA and CE-ATA support
  • SD, including eSD, version 3.0
  • SDIO, including eSDIO, version 3.0
  • CE-ATA - version 1.1
NAND flash controller
  • 1 ONFI 1.0, 8- and 16-bit support
General-purpose I/O (GPIO)
  • Maximum of 48 software programmable GPIO
Timers
  • 4 general-purpose timers
  • 4 watchdog timers
Secure Device Manager Security
  • Secure boot
  • Advanced Encryption Standard (AES) and authentication (SHA/ECDSA)
External Memory Interface External Memory Interface
  • Hard Memory Controller with DDR4 and DDR3
1 Available in some configurations only
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