2024.06.28 |
Removed the register state readback and writeback from the list of key features of Stratix® 10 devices. |
2023.09.07 |
Removed Ethernet AVB from the list of Ethernet standards that the HPS supports. |
2022.08.18 |
Made the following change:
- Updated Important innovations in Intel Stratix 10 FPGAs in GX/SX Device Overview section.
- Updated description for Register state readback and writeback in Key Features of Intel Stratix 10 Devices Compared to Stratix V Devices table.
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2021.04.08 |
Made the following change:
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2020.09.28 |
Made the following change:
- Added black key provisioning (-BK) devices. See the "Sample Ordering Code" figure in Available Options.
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2020.04.30 |
Made the following change:
- Added the GX 10M variant.
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2020.03.24 |
Made the following changes:
- Added advanced security (-AS) devices.
- Added level shifter details for the Stratix® 10 SX/GX 400 device.
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2019.08.19 |
Made the following changes:
- Added composition details for the leaded and lead-free contact device options.
- Updated the I/O PLL counts.
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2019.02.15 |
Made the following changes:
- Changed the number of included logic elements globally.
- Removed logic density 450, logic density 550, and package code 48 from the "Sample Ordering Code and Available Options for Intel Stratix 10 Devices" figure.
- Updated description of the higher density in the "Innovations in Intel Stratix 10 FPGAs and SoCs" section.
- Updated description of the general purpose I/Os in the "Intel Stratix 10 FPGA and SoC Common Device Features" table.
- Removed support for LPDDR3 globally.
- Updated the "Intel Stratix 10 FPGA and SoC Architecture Block Diagram" figure.
- Updated the "Intel Stratix 10 GX/SX FPGA and SoC Family Plan-FPGA Core (part 1)" table.
- Updated the "Intel Stratix 10 GX/SX FPGA and SoC Family Plan-Interconnects, PLLs and Hard IP (part 2)" table.
- Updated and merged the "Intel Stratix 10 GX/SX FPGA and SoC Family Package Plan" tables.
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2018.08.08 |
Made the following changes:
- Changed the specs for QDRII+ and QDRII+ Xtreme and added specs for QDRIV in the "External Memory Interface Performance" table.
- Updated description of the power options in the "Sample Ordering Code and Available Options for Stratix® 10 Devices" figure.
- Changed the description of the technology and power management features in the " Stratix® 10 FPGA and SoC Common Device Features" table.
- Changed the description of SmartVID in the "Power Management" section.
- Changed the direction arrow from the coefficient registers block in the "DSP Block: High Precision Fixed Point Mode" figure.
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2017.10.30 |
Made the following changes:
- Removed the embedded eSRAM feature globally.
- Removed the Low Power (VID) and Military operating temperature options, and package code 53 from the "Sample Ordering Code and Available Options for Stratix 10 Devices" figure.
- Changed the Maximum transceiver data rate (chip-to-chip) specification for L-Tile devices in the "Key Features of Stratix® 10 Devices Compared to Stratix V Devices" table.
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2016.10.31 |
Made the following changes:
- Changed the number of available transceivers to 96, globally.
- Changed the single-precision floating point performance to 10 TFLOP, globally.
- Changed the maximum datarate to 28.3 Gbps, globally.
- Changed some of the features listed in the "Stratix 10 GX/SX Device Overview" section.
- Changed descriptions for the GX and SX devices in the "Stratix 10 Family Variants" section.
- Changed the "Sample Ordering Code and Available Options for Stratix 10 Devices" figure.
- Changed the features listed in the "Key Features of Stratix 10 Devices Compared to Stratix V Devices" table.
- Changed the descriptions of the following areas of the "Stratix 10 FPGA and SoC Common Device Features" table:
- Transceiver hard IP
- Internal memory blocks
- Core clock networks
- Packaging
- Reorganized and updated all tables in the "Stratix 10 FPGA and SoC Family Plan" section.
- Removed the "Migration Between Arria 10 FPGAs and Stratix 10 FPGAs" section.
- Removed footnotes from the "Transceiver PCS Features" table.
- Changed the HMC description in the "External Memory and General Purpose I/O" section.
- Changed the number of fPLLs in the "Fractional Synthesis PLLs and I/O PLLs" section.
- Clarified HMC data width support in the "Key Features of the Stratix 10 HPS" table.
- Changed the description in the "Internal Embedded Memory" section.
- Changed the datarate for the Standard PCS and SDI PCS features in the "Transceiver PCS Features" table.
- Added a note to the "PCI Express Gen1/Gen2/Gen3 Hard IP" section.
- Updated the "Key Features of the Stratix 10 HPS" table.
- Changed the description for the Cache coherency unit in the "Key Features of the Stratix 10 HPS" table.
- Changed the description for the external SDRAM and Flash memory interfaces for HPS in the "Key Features of the Stratix 10 HPS" table.
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2015.12.04 |
Initial release. |