Stratix® 10 GX/SX Device Overview

ID 683729
Date 6/28/2024
Public

1.7. Heterogeneous 3D SiP Transceiver Tiles

Stratix® 10 FPGAs and SoCs feature power efficient, high bandwidth, low latency transceivers. The transceivers are implemented on heterogeneous 3D System-in-Package (SiP) transceiver tiles, each containing 24 full-duplex transceiver channels. In addition to providing a high-performance transceiver solution to meet current connectivity needs, this allows for future flexibility and scalability as data rates, modulation schemes, and protocol IPs evolve.

Figure 6. Monolithic Core Fabric and Heterogeneous 3D SiP Transceiver Tiles
Figure 7. Dual Core Fabric and Heterogeneous 3D SiP Transceiver Tiles (for the Stratix® 10 GX 10M Variant Only)

Each transceiver tile contains:

  • 24 full-duplex transceiver channels (PMA and PCS)10
  • Reference clock distribution network
  • Transmit PLLs
  • High-speed clocking and bonding networks
  • One instance of PCI Express hard IP
Figure 8. Heterogeneous 3D SiP Transceiver Tile Architecture
10 12 full-duplex transceiver channels for the Stratix® 10 GX 10M variant