Stratix® 10 GX/SX Device Overview

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ID 683729
Date 6/28/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 GX/SX Device Overview
1. Stratix® 10 GX/SX Device Overview x
1.1. Stratix® 10 GX/SX Family Variants 1.2. Innovations in Stratix® 10 FPGAs and SoCs 1.3. FPGA and SoC Features Summary 1.4. Stratix® 10 Block Diagram 1.5. Stratix® 10 FPGA and SoC Family Plan 1.6. Hyperflex® Core Architecture 1.7. Heterogeneous 3D SiP Transceiver Tiles 1.8. Stratix® 10 Transceivers 1.9. PCI Express Gen1/Gen2/Gen3 Hard IP 1.10. Interlaken PCS Hard IP 1.11. 10G Ethernet Hard IP 1.12. External Memory and General Purpose I/O 1.13. Adaptive Logic Module (ALM) 1.14. Core Clocking 1.15. Fractional Synthesis PLLs and I/O PLLs 1.16. Internal Embedded Memory 1.17. Variable Precision DSP Block 1.18. Hard Processor System (HPS) 1.19. Power Management 1.20. Device Configuration and Secure Device Manager (SDM) 1.21. Device Security 1.22. Configuration via Protocol Using PCI Express* 1.23. Partial and Dynamic Reconfiguration 1.24. Fast Forward Compile 1.25. Single Event Upset (SEU) Error Detection and Correction 1.26. Document Revision History for the Stratix® 10 GX/SX Device Overview
1.1. Stratix® 10 GX/SX Family Variants x
1.1.1. Available Options
1.8. Stratix® 10 Transceivers x
1.8.1. PMA Features 1.8.2. PCS Features
1.18. Hard Processor System (HPS) x
1.18.1. Key Features of the Stratix® 10 HPS
1. Stratix® 10 GX/SX Device Overview

1.18.1. Key Features of the Stratix® 10 HPS

Table 13.  Key Features of the Stratix® 10 GX/SX HPS

Feature

Description

Quad-core Arm* Cortex* -A53 MPCore processor unit
  • 2.3 MIPS/MHz instruction efficiency
  • CPU frequency up to 1.5 GHz
  • At 1.5 GHz total performance of 13,800 MIPS
  • Arm* v8-A architecture
  • Runs 64 bit and 32 bit Arm* instructions
  • 16 bit and 32 bit Thumb instructions for 30% reduction in memory footprint
  • Jazelle* RCT execution architecture with 8 bit Java byte codes
  • Superscalar, variable length, out-of-order pipeline with dynamic branch prediction
  • Improved Arm* Neon* media processing engine
  • Single- and double-precision floating-point unit
  • Arm* CoreSight* debug and trace technology
System Memory Management Unit
  • Enables a unified memory model and extends hardware virtualization into peripherals implemented in the FPGA fabric
Cache Coherency unit
  • Changes in shared data stored in cache are propagated throughout the system providing bi-directional coherency for co-processing elements.
Cache
  • L1 Cache
    • 32 KB of instruction cache w/ parity check
    • 32 KB of L1 data cache w /ECC
    • Parity checking
  • L2 Cache
    • 1MB shared
    • 8-way set associative
    • SEU Protection with parity on TAG ram and ECC on data RAM
    • Cache lockdown support
On-Chip Memory
  • 256 KB of scratch on-chip RAM
External SDRAM and Flash Memory Interfaces for HPS
  • Hard memory controller with support for DDR4, DDR3
    • 40 bit (32 bit + 8 bit ECC) with select packages supporting 72 bit (64 bit + 8 bit ECC)
    • Support for up to 2666 Mbps DDR4 and 2166 Mbps DDR3 frequencies
    • Error correction code (ECC) support including calculation, error correction, write-back correction, and error counters
    • Software Configurable Priority Scheduling on individual SDRAM bursts
    • Fully programmable timing parameter support for all JEDEC-specified timing parameters
    • Multiport front-end (MPFE) scheduler interface to the hard memory controller, which supports the AXI® Quality of Service (QoS) for interface to the FPGA fabric
  • NAND flash controller
    • ONFI 1.0
    • Integrated descriptor based with DMA
    • Programmable hardware ECC support
    • Support for 8 and 16 bit Flash devices
  • Secure Digital SD/SDIO/MMC controller
    • eMMC 4.5
    • Integrated descriptor based DMA
    • CE-ATA digital commands supported
    • 50 MHz operating frequency
  • Direct memory access (DMA) controller
    • 8-channel
    • Supports up to 32 peripheral handshake interface
Communication Interface Controllers
  • Three 10/100/1000 Ethernet media access controls (MAC) with integrated DMA
    • Supports RGMII and RMII external PHY Interfaces
    • Option to support other PHY interfaces through FPGA logic
      • GMII
      • MII
      • RMII (requires MII to RMII adapter)
      • RGMII (requires GMII to RGMII adapter)
      • SGMII (requires GMII to SGMII adapter)
    • Supports IEEE 1588-2002 and IEEE 1588-2008 standards for precision networked clock synchronization
    • Supports IEEE 802.1Q VLAN tag detection for reception frames
  • Two USB On-the-Go (OTG) controllers with DMA
    • Dual-Role Device (device and host functions)
      • High-speed (480 Mbps)
      • Full-speed (12 Mbps)
      • Low-speed (1.5 Mbps)
      • Supports USB 1.1 (full-speed and low-speed)
    • Integrated descriptor-based scatter-gather DMA
    • Support for external ULPI PHY
    • Up to 16 bidirectional endpoints, including control endpoint
    • Up to 16 host channels
    • Supports generic root hub
    • Configurable to OTG 1.3 and OTG 2.0 modes
  • Five I2C controllers (three can be used by EMAC for MIO to external PHY)
    • Support both 100 Kbps and 400 Kbps modes
    • Support both 7 bit and 10 bit addressing modes
    • Support Master and Slave operating mode
  • Two UART 16550 compatible
    • Programmable baud rate up to 115.2 kilobaud
  • Four serial peripheral interfaces (SPI) (2 Masters, 2 Slaves)
    • Full and Half duplex
Timers and I/O
  • Timers
    • 4 general-purpose timers
    • 4 watchdog timers
  • 48 HPS direct I/O allow HPS peripherals to connect directly to I/O
  • Up to three IO48 banks may be assigned to HPS for HPS DDR access
Interconnect to Logic Core
  • FPGA-to-HPS Bridge
    • Allows IP bus masters in the FPGA fabric to access to HPS bus slaves
    • Configurable 32, 64, or 128 bit AMBA AXI interface
  • HPS-to-FPGA Bridge
    • Allows HPS bus masters to access bus slaves in FPGA fabric
    • Configurable 32, 64, or 128 bit AMBA AXI interface allows high-bandwidth HPS master transactions to FPGA fabric
  • HPS-to-SDM and SDM-to-HPS Bridges
    • Allows the HPS to reach the SDM block and the SDM to bootstrap the HPS
  • Light Weight HPS-to-FPGA Bridge
    • Light weight 32 bit AXI interface suitable for low-latency register accesses from HPS to soft peripherals in FPGA fabric
  • FPGA-to-HPS SDRAM Bridge
    • Up to three AMBA AXI interfaces supporting 32, 64, or 128 bit data paths
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