Stratix® 10 GX/SX Device Overview

Download PDF
ID 683729
Date 6/28/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 GX/SX Device Overview
1. Stratix® 10 GX/SX Device Overview x
1.1. Stratix® 10 GX/SX Family Variants 1.2. Innovations in Stratix® 10 FPGAs and SoCs 1.3. FPGA and SoC Features Summary 1.4. Stratix® 10 Block Diagram 1.5. Stratix® 10 FPGA and SoC Family Plan 1.6. Hyperflex® Core Architecture 1.7. Heterogeneous 3D SiP Transceiver Tiles 1.8. Stratix® 10 Transceivers 1.9. PCI Express Gen1/Gen2/Gen3 Hard IP 1.10. Interlaken PCS Hard IP 1.11. 10G Ethernet Hard IP 1.12. External Memory and General Purpose I/O 1.13. Adaptive Logic Module (ALM) 1.14. Core Clocking 1.15. Fractional Synthesis PLLs and I/O PLLs 1.16. Internal Embedded Memory 1.17. Variable Precision DSP Block 1.18. Hard Processor System (HPS) 1.19. Power Management 1.20. Device Configuration and Secure Device Manager (SDM) 1.21. Device Security 1.22. Configuration via Protocol Using PCI Express* 1.23. Partial and Dynamic Reconfiguration 1.24. Fast Forward Compile 1.25. Single Event Upset (SEU) Error Detection and Correction 1.26. Document Revision History for the Stratix® 10 GX/SX Device Overview
1.1. Stratix® 10 GX/SX Family Variants x
1.1.1. Available Options
1.8. Stratix® 10 Transceivers x
1.8.1. PMA Features 1.8.2. PCS Features
1.18. Hard Processor System (HPS) x
1.18.1. Key Features of the Stratix® 10 HPS
1. Stratix® 10 GX/SX Device Overview

1.13. Adaptive Logic Module (ALM)

Stratix® 10 devices use a similar adaptive logic module (ALM) as the previous generation Arria® 10 and Stratix® V FPGAs, allowing for efficient implementation of logic functions and easy conversion of IP between the devices.

The ALM block diagram shown in the following figure has eight inputs with a fracturable look-up table (LUT), two dedicated embedded adders, and four dedicated registers.

Figure 11.  Stratix® 10 FPGA and SoC ALM Block Diagram


Key features and capabilities of the ALM include:

  • High register count with 4 registers per 8-input fracturable LUT, operating in conjunction with the new Hyperflex® architecture, enables Stratix® 10 devices to maximize core performance at very high core logic utilization
  • Implements select 7-input logic functions, all 6-input logic functions, and two independent functions consisting of smaller LUT sizes (such as two independent 4-input LUTs) to optimize core logic utilization

The Quartus® Prime software takes advantage of the ALM logic structure to deliver the highest performance, optimal logic utilization, and lowest compile times. The Quartus® Prime software simplifies design reuse as it automatically maps legacy designs into the Stratix® 10 ALM architecture.

Level Two Title