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1.1. Release Information for Remote Update Intel® FPGA IP
1.2. Avalon® Memory-Mapped Interface in Remote Update Intel® FPGA IP
1.3. Arria® 10 and Cyclone® 10 GX Devices
1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices
1.5. Cyclone IV and Intel Cyclone 10 LP Devices
1.6. Flash Memory Programming Files
1.7. Design Examples
1.8. Remote Update Intel® FPGA IP User Guide Archives
1.9. Document Revision History for the Remote Update Intel® FPGA IP User Guide
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1.7.2. Cyclone® V Remote Update Design Example
Intel® uses the following hardware and software to create the design example:
- Quartus® Prime Version: 13.0
- Cyclone® V Development Kit with 5CEFA7F31C7ES FPGA Device
Follow these steps to perform the design example tasks:
- Unzip the contents of the design example to your working directory on your PC.
- In the Quartus® Prime software, click Open Project in the File menu.
- Compile the application image:
- Browse to the folder in which you unzipped the files and open the Application_Image.qpf.
- Click Yes in the message box "Do you want to overwrite the database for C:/your working directory/Application_Image.qpf created by Quartus II 64-Bit Version 13.0.a Build 232 Service Pack 1 SJ Full version?"
- On the Processing menu, choose Start Compilation.
- Click OK when the full compilation successful dialog box appears. The Application_Image.sof is generated in c:\<your working directory>\output_files.
- Click close project in the file menu.
- Compile the factory image:
- Browse to the folder in which you unzipped the files and open the SVRSU.qpf.
- Click Yes in the message box "Do you want to overwrite the database for C:/your working directory/Application_Image.qpf created by Quartus II 64-Bit Version 13.0.a Build 232 Service Pack 1 SJ Full version?"
- Choose Start Compilation on the Processing menu.
- Click OK when the full compilation successful dialog box appears. The Factory_Image.sof is generated in c:\<your working directory>\output_files.
- On the File Menu, click Convert Programming Files and select the details as shown below:
- Programming File type: JTAG Indirect Configuration File (.jic)
- Select Configuration Device: EPCQ 128
- Mode: Active Serial x4
- File name: c:/<your working directory>/output_file.jic
- Flash loader: click add device and choose 5CEFA7ES
- SOFT DATA PAGE_0: click Add File and select the factory image file (SVRSU.sof)
- SOFT DATA PAGE_1: click Add File and select the Application image file (Application_Image.sof)
- Click Generate.
- Click OK when the dialog box of .jic file successfully generated appears.
- On the Tool Menu, click Programmer and follow these steps:
- Make sure the board is power up and the Intel® FPGA Download Cable is connected between computer and the board. This design example uses the Intel® FPGA Download Cable and JTAG mode.
- Click Auto Detect.
- Right-click on the 5CEFA7ES and select change file.
- Browse to the output_file.jic that was generated in previous steps.
- Turn on the Program/Configure checkbox and click Start.
- Configuration successful indicates the FPGA is configured successfully.