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1.1. Release Information for Remote Update Intel® FPGA IP
1.2. Avalon® Memory-Mapped Interface in Remote Update Intel® FPGA IP
1.3. Arria® 10 and Cyclone® 10 GX Devices
1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices
1.5. Cyclone IV and Intel Cyclone 10 LP Devices
1.6. Flash Memory Programming Files
1.7. Design Examples
1.8. Remote Update Intel® FPGA IP User Guide Archives
1.9. Document Revision History for the Remote Update Intel® FPGA IP User Guide
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1.5.7.3. Read Source Mapping
Name | Address offset | Read source value |
---|---|---|
RU_MASTER_SM_CURRENT_STATE_MODE | 0x0 0x1 0x2 0x3 |
00 01 10 11 |
RU_FORCE_EARLY_CONF_DONE | 0x4 0x5 0x6 0x7 |
00 01 10 11 |
RU_WATCHDOG_TIMEOUT | 0x8 0x9 0xA 0xB |
00 01 10 11 |
RU_WATCHDOG_ENABLE | 0xC 0xD 0xE 0xF |
00 01 10 11 |
RU_BOOT_ADDRESS | 0x10 0x11 0x12 0x13 |
00 01 10 11 |
RU_FORCE_INTERNAL_OSC | 0x14 0x15 0x16 0x17 |
00 01 10 11 |
RU_RECONFIG_TRIGGER_CONDITIONS | 0x18 0x19 0x1A 0x1B |
00 01 10 11 |
RU_RESET_TIMER | 0x1C | N/A |
RU_RECONFIG | 0x1D | N/A |