Remote Update Intel® FPGA IP User Guide

Download PDF
ID 683695
Date 7/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. Remote Update Intel® FPGA IP User Guide
1. Remote Update Intel® FPGA IP User Guide x
1.1. Release Information for Remote Update Intel® FPGA IP 1.2. Avalon® Memory-Mapped Interface in Remote Update Intel® FPGA IP 1.3. Arria® 10 and Cyclone® 10 GX Devices 1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices 1.5. Cyclone IV and Intel Cyclone 10 LP Devices 1.6. Flash Memory Programming Files 1.7. Design Examples 1.8. Remote Update Intel® FPGA IP User Guide Archives 1.9. Document Revision History for the Remote Update Intel® FPGA IP User Guide
1.3. Arria® 10 and Cyclone® 10 GX Devices x
1.3.1. Remote System Configuration Mode 1.3.2. Remote System Configuration Components 1.3.3. Parameter Settings 1.3.4. Ports 1.3.5. Parameters 1.3.6. Avalon® Memory-Mapped Interface 1.3.7. Enabling Remote System Upgrade Circuitry 1.3.8. Generating Initial RSU Image
1.3.1. Remote System Configuration Mode x
1.3.1.1. Remote System Upgrade State Machine
1.3.1.1. Remote System Upgrade State Machine x
1.3.1.1.1. Switching from Factory to Application Image or from Initial Application Image to Other Application Image
1.3.6. Avalon® Memory-Mapped Interface x
1.3.6.1. Control Status Register Signals 1.3.6.2. Register Map
1.3.6.1. Control Status Register Signals x
1.3.6.1.1. Control Status Register Write Operation 1.3.6.1.2. Control Status Register Read Operation 1.3.6.1.3. Operations Example Waveforms
1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices x
1.4.1. Remote System Configuration Mode 1.4.2. Remote System Configuration Components 1.4.3. Parameter Settings 1.4.4. Ports 1.4.5. Parameters 1.4.6. Avalon® Memory-Mapped Interface 1.4.7. Enabling Remote System Upgrade Circuitry
1.4.6. Avalon® Memory-Mapped Interface x
1.4.6.1. Control Status Register Signals 1.4.6.2. Register Map
1.4.6.1. Control Status Register Signals x
1.4.6.1.1. Control Status Register Write Operation 1.4.6.1.2. Control Status Register Read Operation
1.5. Cyclone IV and Intel Cyclone 10 LP Devices x
1.5.1. Remote System Configuration Mode 1.5.2. Remote System Configuration Components 1.5.3. Parameter Settings 1.5.4. Ports 1.5.5. Parameters 1.5.6. Remote Update Operation 1.5.7. Avalon® Memory-Mapped Interface 1.5.8. Enabling Remote System Upgrade Circuitry
1.5.7. Avalon® Memory-Mapped Interface x
1.5.7.1. Control Status Register Signals 1.5.7.2. Register Map 1.5.7.3. Read Source Mapping
1.5.7.1. Control Status Register Signals x
1.5.7.1.1. Control Status Register Write Operation 1.5.7.1.2. Control Status Register Read Operation
1.7. Design Examples x
1.7.1. Intel Arria 10 Remote Update Design Example 1.7.2. Cyclone® V Remote Update Design Example
1. Remote Update Intel® FPGA IP User Guide

1.4.5. Parameters

Table 11.  Parameter Type and Corresponding Parameter Bit Width Mapping for Arria® II, Arria® V, Cyclone® V, Stratix® IV, and Stratix® V Devices
Bit Parameter Width Comments
000 Reconfiguration trigger conditions (Read Only) 5
  • Bit 4—wdtimer_source: User watchdog timer timeout.
  • Bit 3—nconfig_source: External configuration reset (nCONFIG) assertion.
  • Bit 2—runconfig_source: Configuration reset triggered from logic array.
  • Bit 1—nstatus_source: nSTATUS asserted by an external device as the result of an error.
  • Bit 0—crcerror_source: CRC error during application configuration.

The POR value for all bits are 0.

001 Illegal Value
010 Watchdog Timeout Value 12 Width of 12 when writing.

The 12 bits for writing are the upper 12 bits (left-most or most-significant bits) of the 29-bit Watchdog Timeout Value.

When writing parameter data, data_in[11..0] corresponds to the upper 12 bits of the 29-bit Watchdog Timeout Value. For example, to set the Watchdog Timeout Value to 1, write the 12 bits of data_in[11..0] as 12'b000000000001.

29 Width of 29 when reading.
011 Watchdog Enable 1 —
100 Page Select 24 or 32

For the Quartus® Prime software version 13.1 and later:

  • Width of 24 or 32 when reading and writing the start address.
  • For active serial devices using 24-bit addressing, such as EPCS128 or EPCQ128, PGM[23..2] corresponds to the upper 22 bits of the 24-bits start address. PGM[1..0] is read as 2'b0.
  • For active serial devices using 32-bit addressing, such as EPCQ256, PGM[31..2] corresponds to the upper 30 bits of the 32-bits start address. PGM[1..0] is read as 2'b0.

For the Quartus® Prime software version 13.0 and earlier:

  • Width of 24 when reading and writing the start address.
  • For Arria® II and Stratix® IV devices, PGM[23..0] form the 24-bit start address.
  • For Arria® V, Cyclone® V, and Stratix® V devices, if you use active serial devices using 24-bit addressing, such as EPCS128 or EPCQ128, PGM[23..0] corresponds to the 24 bits of the start address. If you use active serial devices using 32-bit addressing, such as EPCQ256, PGM[23..0] corresponds to the 24 MSB of the start address, thus the 32 bits start address is PGM[23..0],8'b0.
101 Configuration Mode (AnF) 1

This parameter is set to 1 in application page and is set to 0 in factory page. In remote update mode, this parameter can be read and written.

Before loading the application page in remote update mode, Intel® recommends that you set this parameter to 1. The content of the control register cannot be read properly if you fail to do so.

110 Illegal Value
111 Illegal Value
Level Two Title