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1.1. Release Information for Remote Update Intel® FPGA IP
1.2. Avalon® Memory-Mapped Interface in Remote Update Intel® FPGA IP
1.3. Arria® 10 and Cyclone® 10 GX Devices
1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices
1.5. Cyclone IV and Intel Cyclone 10 LP Devices
1.6. Flash Memory Programming Files
1.7. Design Examples
1.8. Remote Update Intel® FPGA IP User Guide Archives
1.9. Document Revision History for the Remote Update Intel® FPGA IP User Guide
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1.6. Flash Memory Programming Files
You can program the flash memory, EPCS, EPCQ, and EPCQ-L using the JTAG interface or Active Serial interface. Depending on the interface, you need to generate either a JTAG indirect configuration (.jic) file or a raw programming data (.rpd) file.
Programming Interface | Flash Memory Programming File Used | Description |
---|---|---|
JTAG Interface | .jic | The .jic file instantiates the Serial Flash Loader IP core in the design to form a bridge between the flash and the JTAG Interface. |
Active Serial Interface | .rpd | Programming data is transferred directly between the flash and download cable. |
To update the application image only, you can do either one of the following:
- Recompile the .jic file and choose new application image only in the convert programming file tool.
- Generate the .rpd file and program the EPCQ-L with ASMI IP or external controller.