Remote Update Intel® FPGA IP User Guide

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ID 683695
Date 7/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. Remote Update Intel® FPGA IP User Guide
1. Remote Update Intel® FPGA IP User Guide x
1.1. Release Information for Remote Update Intel® FPGA IP 1.2. Avalon® Memory-Mapped Interface in Remote Update Intel® FPGA IP 1.3. Arria® 10 and Cyclone® 10 GX Devices 1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices 1.5. Cyclone IV and Intel Cyclone 10 LP Devices 1.6. Flash Memory Programming Files 1.7. Design Examples 1.8. Remote Update Intel® FPGA IP User Guide Archives 1.9. Document Revision History for the Remote Update Intel® FPGA IP User Guide
1.3. Arria® 10 and Cyclone® 10 GX Devices x
1.3.1. Remote System Configuration Mode 1.3.2. Remote System Configuration Components 1.3.3. Parameter Settings 1.3.4. Ports 1.3.5. Parameters 1.3.6. Avalon® Memory-Mapped Interface 1.3.7. Enabling Remote System Upgrade Circuitry 1.3.8. Generating Initial RSU Image
1.3.1. Remote System Configuration Mode x
1.3.1.1. Remote System Upgrade State Machine
1.3.1.1. Remote System Upgrade State Machine x
1.3.1.1.1. Switching from Factory to Application Image or from Initial Application Image to Other Application Image
1.3.6. Avalon® Memory-Mapped Interface x
1.3.6.1. Control Status Register Signals 1.3.6.2. Register Map
1.3.6.1. Control Status Register Signals x
1.3.6.1.1. Control Status Register Write Operation 1.3.6.1.2. Control Status Register Read Operation 1.3.6.1.3. Operations Example Waveforms
1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices x
1.4.1. Remote System Configuration Mode 1.4.2. Remote System Configuration Components 1.4.3. Parameter Settings 1.4.4. Ports 1.4.5. Parameters 1.4.6. Avalon® Memory-Mapped Interface 1.4.7. Enabling Remote System Upgrade Circuitry
1.4.6. Avalon® Memory-Mapped Interface x
1.4.6.1. Control Status Register Signals 1.4.6.2. Register Map
1.4.6.1. Control Status Register Signals x
1.4.6.1.1. Control Status Register Write Operation 1.4.6.1.2. Control Status Register Read Operation
1.5. Cyclone IV and Intel Cyclone 10 LP Devices x
1.5.1. Remote System Configuration Mode 1.5.2. Remote System Configuration Components 1.5.3. Parameter Settings 1.5.4. Ports 1.5.5. Parameters 1.5.6. Remote Update Operation read_source 1.5.7. Avalon® Memory-Mapped Interface 1.5.8. Enabling Remote System Upgrade Circuitry
1.5.7. Avalon® Memory-Mapped Interface x
1.5.7.1. Control Status Register Signals 1.5.7.2. Register Map 1.5.7.3. Read Source Mapping
1.5.7.1. Control Status Register Signals x
1.5.7.1.1. Control Status Register Write Operation 1.5.7.1.2. Control Status Register Read Operation
1.7. Design Examples x
1.7.1. Intel Arria 10 Remote Update Design Example 1.7.2. Cyclone® V Remote Update Design Example
1. Remote Update Intel® FPGA IP User Guide

1.5.6. Remote Update Operation

The operation defined in the Remote Update Operation column should only be performed in the corresponding master state machine (MSM) mode.

Table 18.   Cyclone® IV and Cyclone® 10 LP Devices Remote Update Operation
Note: read_source specifies whether a parameter value is read from the current or a previous state. For more information, refer to Table 19.
read_ param write_ param read_source param Remote Update Operation data_out width (bits) MSM Mode
1 0 [00] [000] Master State Machine Current State Mode (Read Only)
  • 00—Factory mode
  • 01—Application mode
  • 11—Application mode with master state machine user watchdog timer enabled
2 Factory or Application
1 0 [00] [100] Read factory boot address 24 Factory
1 0 [01] [100]

Read Past Status 1 boot address.

For more information, refer to Figure 11.

24 Factory
1 0 [01] [111]

Read Past Status 1 reconfiguration trigger condition source.

For more information, refer to Figure 11.

5 Factory
1 0 [10] [100]

Read Past Status 2 boot address.

For more information, refer to Figure 11.

24 Factory
1 0 [10] [111]

Read Past Status 2 reconfiguration trigger condition source

For more information, refer to Figure 11.

5 Factory
1 0 [01] [010] Read current application mode watchdog value 29 Application
1 0 [01] [011] Read current application mode watchdog enable 1 Application
1 0 [10] [100] Read current application mode boot address 24 Application
0 1 [00] [001]

Write the early confdone check bit.

All parameters can be written in factory mode only.

1 Factory
0 1 [00] [010]

Write the watchdog time-out value.

All parameters can be written in factory mode only.

12 Factory
0 1 [00] [011]

Write the watchdog enable bit.

All parameters can be written in factory mode only.

1 Factory
0 1 [00] [100]

Write application boot address.

All parameters can be written in factory mode only.

22 Factory
0 1 [00] [110] Write to force the internal oscillator as startup state machine clock. All parameters can be written in factory mode only. 1 Factory
1 0 [11] [001] Read the early confdone check bits 1 Factory
1 0 [11] [010] Read watchdog time-out value 12 Factory
1 0 [11] [011] Read watchdog enable bit 1 Factory
1 0 [11] [100] Read boot address 22 Factory
1 0 [11] [110] Read to check whether the internal oscillator is set as startup state machine clock 1 Factory

read_source

The following table lists the details for read_source. read_source specifies whether a parameter value is read from the current or a previous state. When you trigger the read operation, all contents in the status register or input register latched to the data_out node in the Remote Update Intel® FPGA IP core.

Table 19.  read_source
read_source Description
00 Current state contents in status register
01 Previous state register 1 contents in status register
10 Previous state register 2 contents in status register
11 Current contents is in input register

The previous state register 1 reflects the current application configuration and the previous state register 2 reflects the previous application configuration.

Figure 11. State Register


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