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1.1. Release Information for Remote Update Intel® FPGA IP
1.2. Avalon® Memory-Mapped Interface in Remote Update Intel® FPGA IP
1.3. Arria® 10 and Cyclone® 10 GX Devices
1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices
1.5. Cyclone IV and Intel Cyclone 10 LP Devices
1.6. Flash Memory Programming Files
1.7. Design Examples
1.8. Remote Update Intel® FPGA IP User Guide Archives
1.9. Document Revision History for the Remote Update Intel® FPGA IP User Guide
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1.3.6.1.3. Operations Example Waveforms
Note: Intel® recommends that you verify the Remote Update Intel FPGA IP core for Arria® 10 and Cyclone® 10 GX devices in hardware because the simulation model is not supported for Remote Update Intel® FPGA IP core for Arria® 10 and Cyclone® 10 GX devices.
Figure 5. Waveform for Write Operation
Figure 6. Waveform for Read Operation
Figure 7. Waveform for RU_CTL_NUPDT OperationThe RU_CTL_NUPDT will hold the value until a new value is inserted.
Figure 8. Waveform for Reset Timer and Reconfiguration OperationThe RU_RECONFIG will hold the value until the reconfiguration process is done.