Remote Update Intel® FPGA IP User Guide

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ID 683695
Date 7/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. Remote Update Intel® FPGA IP User Guide
1. Remote Update Intel® FPGA IP User Guide x
1.1. Release Information for Remote Update Intel® FPGA IP 1.2. Avalon® Memory-Mapped Interface in Remote Update Intel® FPGA IP 1.3. Arria® 10 and Cyclone® 10 GX Devices 1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices 1.5. Cyclone IV and Intel Cyclone 10 LP Devices 1.6. Flash Memory Programming Files 1.7. Design Examples 1.8. Remote Update Intel® FPGA IP User Guide Archives 1.9. Document Revision History for the Remote Update Intel® FPGA IP User Guide
1.3. Arria® 10 and Cyclone® 10 GX Devices x
1.3.1. Remote System Configuration Mode 1.3.2. Remote System Configuration Components 1.3.3. Parameter Settings 1.3.4. Ports 1.3.5. Parameters 1.3.6. Avalon® Memory-Mapped Interface 1.3.7. Enabling Remote System Upgrade Circuitry 1.3.8. Generating Initial RSU Image
1.3.1. Remote System Configuration Mode x
1.3.1.1. Remote System Upgrade State Machine
1.3.1.1. Remote System Upgrade State Machine x
1.3.1.1.1. Switching from Factory to Application Image or from Initial Application Image to Other Application Image
1.3.6. Avalon® Memory-Mapped Interface x
1.3.6.1. Control Status Register Signals 1.3.6.2. Register Map
1.3.6.1. Control Status Register Signals x
1.3.6.1.1. Control Status Register Write Operation 1.3.6.1.2. Control Status Register Read Operation 1.3.6.1.3. Operations Example Waveforms
1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices x
1.4.1. Remote System Configuration Mode 1.4.2. Remote System Configuration Components 1.4.3. Parameter Settings 1.4.4. Ports 1.4.5. Parameters 1.4.6. Avalon® Memory-Mapped Interface 1.4.7. Enabling Remote System Upgrade Circuitry
1.4.6. Avalon® Memory-Mapped Interface x
1.4.6.1. Control Status Register Signals 1.4.6.2. Register Map
1.4.6.1. Control Status Register Signals x
1.4.6.1.1. Control Status Register Write Operation 1.4.6.1.2. Control Status Register Read Operation
1.5. Cyclone IV and Intel Cyclone 10 LP Devices x
1.5.1. Remote System Configuration Mode 1.5.2. Remote System Configuration Components 1.5.3. Parameter Settings 1.5.4. Ports 1.5.5. Parameters 1.5.6. Remote Update Operation 1.5.7. Avalon® Memory-Mapped Interface 1.5.8. Enabling Remote System Upgrade Circuitry
1.5.7. Avalon® Memory-Mapped Interface x
1.5.7.1. Control Status Register Signals 1.5.7.2. Register Map 1.5.7.3. Read Source Mapping
1.5.7.1. Control Status Register Signals x
1.5.7.1.1. Control Status Register Write Operation 1.5.7.1.2. Control Status Register Read Operation
1.7. Design Examples x
1.7.1. Intel Arria 10 Remote Update Design Example 1.7.2. Cyclone® V Remote Update Design Example
1. Remote Update Intel® FPGA IP User Guide

1.9. Document Revision History for the Remote Update Intel® FPGA IP User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.07.25 19.4 19.1.0 Changed width for avl_csr_address in the Control Status Register Signals section.
2023.11.29 19.4 19.1.0
  • Added new topic—Release Information for Remote Update Intel® FPGA IP .
  • Updated for the latest branding standards.
  • Made editorial edits throughout the document.
  • Updated note in Remote System Configuration Mode section.
  • Updated Remote Update Intel® FPGA IP User Guide Archives section.
  • Added additional values for configuration device in Remote Update Intel® FPGA IP Core Parameters for Arria® 10 and Cyclone® 10 GX Devices table in Parameter Settings section.
  • Added additional values for configuration device in Remote Update Intel® FPGA IP Core Parameters for Arria® II, Arria® V, Cyclone® V, Stratix® IV, and Stratix® V Devices table in Parameter Settings section.
Document Version Quartus® Prime Version Changes
2022.08.16 18.0
  • Added note in Transitions Between Factory and Application Configurations in Remote Update Mode figure.
  • Updated details for SOF DATA PAGE_0: click Add File and assign Factory image (.sof) to Page_0 in Generating Initial RSU Image section.
2021.07.13 18.0
  • Added new note describing the fallback to the factory image in the Remote System Configuration Mode topic.
  • Updated the POF checking feature description in the Parameter Settings topic.
2020.02.11 18.0 Updated the Enabling Remote System Upgrade Circuitry topic.
2019.12.24 18.0
  • Updated the Arria® 10 and Cyclone® 10 Devices section:
    • Added new topic: Generating Initial RSU Image
    • Updated the description of the Remote System Configuration Mode topic.
2019.10.22 18.0
  • Added new topics:
    • Remote System Upgrade State Machine
    • Switching from Factory to Application Image or from Initial Application Image to Other Application Image
2019.04.26 18.0
  • Added support information for Cyclone® 10 GX and LP devices.
  • Updated label for active parallel configuration scheme to "Cyclone IV E devices only" in Figure: High-Level Block Diagram of Remote System Upgrade.
  • Updated details for page mode feature and factory configuration components in Table: Remote System Configuration Components in Cyclone® IV and Cyclone® 10 LP Devices so that AP configuration only applies to Cyclone® IV E devices.
  • Updated Watchdog Timer details by adding "left-most or most-significant bits" to enhance clarity of "upper 12 bits" in Table: Remote System Configuration Components in Intel Arria 10 and Intel Cyclone 10 GX Devices, Table: Remote System Configuration Components in Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices, and Table: Remote System Configuration Components in Cyclone IV and Intel Cyclone 10 LP Devices.
  • Added width of 29 and comments to Watchdog Timeout Value in Table: Parameter Type and Corresponding Parameter Bit Width Mapping for Intel Arria 10 and Intel Cyclone 10 GX Devices and Table: Parameter Type and Corresponding Parameter Bit Width Mapping for Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices.
  • Updated Watchdog Timeout Value comments by adding "left-most or most-significant bits" to enhance clarity of "upper 12 bits" and statements on bit mapping between data_in and the 12-bit watchdog timeout value in Table: Parameter Type and Corresponding Parameter Bit Width Mapping for Cyclone IV and Intel Cyclone 10 LP Devices.
2019.01.09 18.0
  • Updated the table description in Table: Remote Update Intel® FPGA IP Core Avalon® -MM Register Map for Cyclone® IV Devices.
2018.11.26 18.0
  • Renamed the document as Remote Update Intel® FPGA IP User Guide.
  • Updated Figure: Typical Remote System Upgrade Process.
  • Updated the note under Figure: Typical Remote System Upgrade Process.
  • Added a note to Operations Example Waveforms.
  • Updated Table: Remote Update Intel® FPGA IP Core Parameters for Arria® 10 Devices to update the description for Enable reconfig POF checking.
  • Rebranded as Intel.
Table 24.  Document Revision History
Date Version Changes
April 2017 2017.04.10
  • Updated Transitions Between Factory and Application Configurations in Remote Update Mode figure.
  • Removed redundant statement in Avalon-MM in Altera Remote Update IP Core.
  • Updated note in Remote Update Operation table.
October 2016 2016.10.31
  • Updated Parameters table for Arria 10 devices and Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices.
  • Added Add support for Avalon Interface parameter in Parameter Settings tables.
June 2016 2016.06.01
  • Updated Convert Programming File settings in Arria 10 Remote Update Design Example.
  • Removed references to Local update mode features.
May 2016 2016.05.02
  • Added recommended FMAX for Altera Remote Update IP core.
  • Added missing title for Cyclone IV Devices Remote Update Operation table.
  • Added note on possible PCIe timing violation when using direct-to-application.
  • Added note on recommending user to set a fixed configuration image start address.
  • Added Enabling Remote System Upgrade subsection.
December 2015 2015.12.14 Updated RU_RECONFIG_TRIGGER_CONDITIONS description for Cyclone V Avalon-MM interface register.
November 2015 2015.11.17
  • Updated Page description in Convert Programming Files setting from SOFT DATA PAGE_0 to SOFT DATA PAGE_1.
  • Added high level configuration scheme block diagram for remote system upgrade.
  • Added Flash Memory Programming Files.
  • Added design example for Arria 10 devices.
June 2015 2015.06.15
  • Added Avalon-MM interface support for Quartus II Software version 15.0.
  • Added table for Avalon-MM interface Control Status Registers and register map definitions.
  • Added steps for read and write operation for Avalon-MM interface.
  • Added example waveforms for read, write, reset timer, ctl_nupdt, and reconfiguration operation for Arria 10 devices.
  • Updated the Device Support section to include information on device families that will be phased out from Quartus II software version 15.0.
April 2015 2015.04.07 Added design example link.
January 2015 2015.01.23 Updated Arria 10 remote system configuration mode flow diagram.
December 2014 2014.12.15
  • Updated POF checking feature description and invalid configuration image examples.
  • Added Arria 10 device support with descriptions, ports and parameters.
  • Replaced outdated design examples with a current application design example.
June 2014 2014.06.30
  • Replaced MegaWizard Plug-In Manager information with IP Catalog.
  • Added standard information about upgrading IP cores.
  • Added standard installation and licensing information.
  • Removed outdated device support level information. IP core device support is now available in IP Catalog and parameter editor.
  • Added a note to recommend users to use 20–MHz fMAX for all devices.
May 2014 2014.05.13
  • Updated the Device Support section to include information on device families that will be phased out from Quartus II software version 13.1 and Quartus II software version 14.0.
  • Rearranged content for remote system configuration modes, remote system configuration components, parameter settings, ports, param for each group of devices. Refer to Device Support section for more information.
August 2013 2013.08.16 Added Cyclone IV devices support for Active Serial Remote Configuration Mode in Parameters, Output Ports, and Active Serial Remote Configuration Mode.
July 2013 2013.07.12
  • Updated Watchdog Timer to include the watchdog reset_time requirement to ensure the validity of the application configuration. Listed the supported devices for the watchdog timer feature.
  • Updated Device Support section.
  • Added Active Serial Remote Configuration Mode to clarify that the active serial configuration mode is a subset of the remote configuration mode. Also clarified that this mode is only available for EPCS devices.
  • Added a link to the Configuration Handbook in the Remote System Configuration Modes.
  • Updated Remote Configuration Mode to add that Cyclone IV E devices support AP configuration scheme and included a link to the Configuration and Remote System Upgrades in Cyclone IV Devices chapter.
  • Updated Remote System Configuration Components to clarify that the local configuration mode does not support the user watchdog timer feature.
  • Included a cross-reference to the Input Port in Page Mode Feature.
  • Updated Parameters to update values and supported devices of the GUI parameter settings.
  • Updated Factory Configuration to clarify that the default factory configuration address does not apply for Cyclone V devices.
July 2013 2013.07.12
  • Added Cyclone III and Cyclone IV Devices Remote Update Operation.
  • Updated Input Ports to include Arria V and Cyclone V support for data_in[] port.
  • Added Param[] as a standalone section.
  • Updated Parameter Type and Corresponding Parameter Bit Width Mapping to include Arria V and Cyclone V support for Reconfiguration trigger conditions parameter. Also updated Page Select parameter to include information for Arria V, Cyclone V, and Stratix V devices.
  • Updated Parameter Type and Corresponding Parameter Bit Width Mapping to update the Configuration Mode (AnF) information.
  • Updated Input Ports to add a link to the Configuration, Design Security, and Remote Upgrades in the Cyclone III Device Family chapter.
  • Updated Input Ports to clarify that a falling edge of the reset_timer signal triggers a reset of the user watchdog timer.
  • Updated Output Ports to add Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V device support for 24-bit bus for data_out[] port.
  • Added Knowledge Base section.
  • Added Simulation to clarify that simulation capability are for Arria GX, Stratix, and Stratix II devices only.
February 2012 3.0 Add Cyclone IV support for param[] parameter.
August 2010 2.5

Updated for Quartus II software v10.0, including:

  • Updated the Device Family Support section.
  • Add Parameters table to Specifications chapter.
  • Added new parameters and ports to Specifications chapter.
  • Added new prototypes and declarations sections to Specifications chapter.
  • Updated design example figures and steps.
April 2009 2.4

Updated for Quartus II software v9.0, including:

  • Updated the section.
  • Added the Maximum Clock Frequency (fMAX) for the supported devices.
  • Updated ports and parameter tables.
May 2007 2.3

Updated for Quartus II software v7.1, including:

  • Updated to include support for Arria® GX devices.
  • Updated to include Cyclone® III device information.
  • Added Referenced Documents section.
March 2007 2.2 Updated Chapter 1 to include Cyclone III support.
December 2006 2.1 Updated Chapter 1 to include Stratix® III support.
September 2006 2.0 General update for Quartus II software version 6.0, including screenshots; added ModelSim®-Altera simulation tool section to Chapter 3.
March 2005 1.0 Initial release.
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