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1.1. Release Information for Remote Update Intel® FPGA IP
1.2. Avalon® Memory-Mapped Interface in Remote Update Intel® FPGA IP
1.3. Arria® 10 and Cyclone® 10 GX Devices
1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices
1.5. Cyclone IV and Intel Cyclone 10 LP Devices
1.6. Flash Memory Programming Files
1.7. Design Examples
1.8. Remote Update Intel® FPGA IP User Guide Archives
1.9. Document Revision History for the Remote Update Intel® FPGA IP User Guide
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1.3.1.1.1. Switching from Factory to Application Image or from Initial Application Image to Other Application Image
Follow these steps to switch from factory to application image or from initial application image to other application image:
- Write the AnF bit to 1 via RU_RECONFIG register.
- Write the start address of the application image to be loaded via the RU_PAGE_SELECT register.
- Enable the watchdog timer settings:
- Write the timeout value to RU_WATCHDOG_TIMEOUT register.
- Enable watchdog timeout via RU_WATCHDOG_ENABLE register.
- Writes RU_RECONFIG to “1” to trigger reconfiguration to application image. After successful reconfiguration, the system stays in the application configuration. If error occurs during reconfiguration, the RSU state machine falls back to the factory image.
- Optional step. Read the configuration status via the RU_RECONFIG_TRIGGER_CONDITIONS register.
- Write a falling edge signal to reset the watchdog timer.
- Repeat steps 1 to 6 to perform remote update to other application image.
Note: It is optional to instantiate the Remote Update Intel® FPGA IP core in the application image if you do not need to update the application image in user mode. Without this IP core instantiated in the application image, the device is still able to revert back to factory image if there is an error in loading the application image.