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1.1. Release Information for Remote Update Intel® FPGA IP
1.2. Avalon® Memory-Mapped Interface in Remote Update Intel® FPGA IP
1.3. Arria® 10 and Cyclone® 10 GX Devices
1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices
1.5. Cyclone IV and Intel Cyclone 10 LP Devices
1.6. Flash Memory Programming Files
1.7. Design Examples
1.8. Remote Update Intel® FPGA IP User Guide Archives
1.9. Document Revision History for the Remote Update Intel® FPGA IP User Guide
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1.2. Avalon® Memory-Mapped Interface in Remote Update Intel® FPGA IP
The Avalon® memory-mapped interface is supported in the Remote Update Intel® FPGA IP. You can only use the IP core either with or without Avalon® memory-mapped interface. You can instantiate the Avalon® memory-mapped interface by turning on the Add support for Avalon Interface option in the Remote Update Intel® FPGA IP parameter editor.
Note: The Avalon® memory-mapped interface support for Remote Update Intel® FPGA IP is available in Quartus® Prime software version 15.0 and onwards.
Figure 3. Remote Update Intel® FPGA IP Implementation with and without Avalon® Memory-Mapped InterfaceeThis figure shows the Avalon® Remote update support architecture, which consists of two components; Remote Update Intel® FPGA IP and Avalon® remote update controller. If the Avalon® interface is enabled, the conduit interfaces of the Remote Update Intel® FPGA IP connects to the conduit interface of the controller.